Subversion Repositories usb_nand_reader

_init_nand_control_line:
;NandControl.c,27 ::            void init_nand_control_line()
;NandControl.c,29 ::            TRISB0_bit = 1;
LUI     R2, BitMask(TRISB0_bit+0)
ORI     R2, R2, BitMask(TRISB0_bit+0)
_SX     
;NandControl.c,30 ::            TRISD11_bit = 1;
LUI     R2, BitMask(TRISD11_bit+0)
ORI     R2, R2, BitMask(TRISD11_bit+0)
_SX     
;NandControl.c,31 ::            TRISB9_bit = 1;
LUI     R2, BitMask(TRISB9_bit+0)
ORI     R2, R2, BitMask(TRISB9_bit+0)
_SX     
;NandControl.c,32 ::            TRISD5_bit = 1;
LUI     R2, BitMask(TRISD5_bit+0)
ORI     R2, R2, BitMask(TRISD5_bit+0)
_SX     
;NandControl.c,34 ::            TRISB14_bit = 0;
LUI     R2, BitMask(TRISB14_bit+0)
ORI     R2, R2, BitMask(TRISB14_bit+0)
_SX     
;NandControl.c,35 ::            TRISF0_bit = 0;
LUI     R2, BitMask(TRISF0_bit+0)
ORI     R2, R2, BitMask(TRISF0_bit+0)
_SX     
;NandControl.c,36 ::            TRISF1_bit = 0;
LUI     R2, BitMask(TRISF1_bit+0)
ORI     R2, R2, BitMask(TRISF1_bit+0)
_SX     
;NandControl.c,37 ::            TRISB8_bit = 0;
LUI     R2, BitMask(TRISB8_bit+0)
ORI     R2, R2, BitMask(TRISB8_bit+0)
_SX     
;NandControl.c,39 ::            TRISD4_bit = 0;
LUI     R2, BitMask(TRISD4_bit+0)
ORI     R2, R2, BitMask(TRISD4_bit+0)
_SX     
;NandControl.c,40 ::            TRISB15_bit = 0;
LUI     R2, BitMask(TRISB15_bit+0)
ORI     R2, R2, BitMask(TRISB15_bit+0)
_SX     
;NandControl.c,41 ::            TRISD0_bit = 0;
LUI     R2, BitMask(TRISD0_bit+0)
ORI     R2, R2, BitMask(TRISD0_bit+0)
_SX     
;NandControl.c,42 ::            TRISE0_bit = 0;
LUI     R2, BitMask(TRISE0_bit+0)
ORI     R2, R2, BitMask(TRISE0_bit+0)
_SX     
;NandControl.c,43 ::            TRISE1_bit = 0;
LUI     R2, BitMask(TRISE1_bit+0)
ORI     R2, R2, BitMask(TRISE1_bit+0)
_SX     
;NandControl.c,45 ::            ctrl_nce0 = 1;
LUI     R2, BitMask(LATB8_bit+0)
ORI     R2, R2, BitMask(LATB8_bit+0)
_SX     
;NandControl.c,46 ::            ctrl_nce1 = 1;
LUI     R2, BitMask(LATF1_bit+0)
ORI     R2, R2, BitMask(LATF1_bit+0)
_SX     
;NandControl.c,47 ::            ctrl_nce2 = 1;
LUI     R2, BitMask(LATF0_bit+0)
ORI     R2, R2, BitMask(LATF0_bit+0)
_SX     
;NandControl.c,48 ::            ctrl_nce3 = 1;
LUI     R2, BitMask(LATB14_bit+0)
ORI     R2, R2, BitMask(LATB14_bit+0)
_SX     
;NandControl.c,50 ::            ctrl_nre = 1;
LUI     R2, BitMask(LATD4_bit+0)
ORI     R2, R2, BitMask(LATD4_bit+0)
_SX     
;NandControl.c,51 ::            ctrl_cle = 0;
LUI     R2, BitMask(LATB15_bit+0)
ORI     R2, R2, BitMask(LATB15_bit+0)
_SX     
;NandControl.c,52 ::            ctrl_ale = 0;
LUI     R2, BitMask(LATD0_bit+0)
ORI     R2, R2, BitMask(LATD0_bit+0)
_SX     
;NandControl.c,53 ::            ctrl_nwe = 1;
LUI     R2, BitMask(LATE0_bit+0)
ORI     R2, R2, BitMask(LATE0_bit+0)
_SX     
;NandControl.c,54 ::            ctrl_nwp = 0;
LUI     R2, BitMask(LATE1_bit+0)
ORI     R2, R2, BitMask(LATE1_bit+0)
_SX     
;NandControl.c,55 ::            }
L_end_init_nand_control_line:
JR      RA
NOP     
; end of _init_nand_control_line
_nand_is_ready:
;NandControl.c,57 ::            int nand_is_ready()
;NandControl.c,59 ::            int r = (int)(ctrl_rnb0 & ctrl_rnb1 & ctrl_rnb2 & ctrl_rnb3);
LBU     R2, Offset(PORTD+0)(GP)
EXT     R2, R2, 5, 1
ANDI    R3, R2, 255
LBU     R2, Offset(PORTB+1)(GP)
EXT     R2, R2, 1, 1
AND     R3, R3, R2
LBU     R2, Offset(PORTD+1)(GP)
EXT     R2, R2, 3, 1
AND     R3, R3, R2
LBU     R2, Offset(PORTB+0)(GP)
EXT     R2, R2, 0, 1
AND     R2, R3, R2
ANDI    R2, R2, 255
; r start address is: 12 (R3)
SEH     R3, R2
;NandControl.c,60 ::            if(0 == r)
SEH     R2, R2
BEQ     R2, R0, L__nand_is_ready30
NOP     
J       L_nand_is_ready0
NOP     
L__nand_is_ready30:
;NandControl.c,61 ::            LATG6_bit = 0;
LUI     R2, BitMask(LATG6_bit+0)
ORI     R2, R2, BitMask(LATG6_bit+0)
_SX     
J       L_nand_is_ready1
NOP     
L_nand_is_ready0:
;NandControl.c,63 ::            LATG6_bit = 1;
LUI     R2, BitMask(LATG6_bit+0)
ORI     R2, R2, BitMask(LATG6_bit+0)
_SX     
L_nand_is_ready1:
;NandControl.c,64 ::            return r;
SEH     R2, R3
; r end address is: 12 (R3)
;NandControl.c,65 ::            }
L_end_nand_is_ready:
JR      RA
NOP     
; end of _nand_is_ready
_nand_wait_ready:
;NandControl.c,67 ::            void nand_wait_ready()
ADDIU   SP, SP, -4
SW      RA, 0(SP)
;NandControl.c,69 ::            while(0 == nand_is_ready());
L_nand_wait_ready2:
JAL     _nand_is_ready+0
NOP     
SEH     R2, R2
BEQ     R2, R0, L__nand_wait_ready32
NOP     
J       L_nand_wait_ready3
NOP     
L__nand_wait_ready32:
J       L_nand_wait_ready2
NOP     
L_nand_wait_ready3:
;NandControl.c,70 ::            }
L_end_nand_wait_ready:
LW      RA, 0(SP)
ADDIU   SP, SP, 4
JR      RA
NOP     
; end of _nand_wait_ready
_nand_chip_select:
;NandControl.c,72 ::            void nand_chip_select(int idx)
;NandControl.c,74 ::            switch(idx)
J       L_nand_chip_select4
NOP     
;NandControl.c,76 ::            case 0:
L_nand_chip_select6:
;NandControl.c,77 ::            ctrl_nce1 = ctrl_nce2 = ctrl_nce3 = 1;
LUI     R2, BitMask(LATB14_bit+0)
ORI     R2, R2, BitMask(LATB14_bit+0)
_SX     
_LX     
EXT     R3, R2, BitPos(LATB14_bit+0), 1
_LX     
INS     R2, R3, BitPos(LATF0_bit+0), 1
_SX     
_LX     
EXT     R3, R2, BitPos(LATF0_bit+0), 1
_LX     
INS     R2, R3, BitPos(LATF1_bit+0), 1
_SX     
;NandControl.c,78 ::            ctrl_nce0 = 0;
LUI     R2, BitMask(LATB8_bit+0)
ORI     R2, R2, BitMask(LATB8_bit+0)
_SX     
;NandControl.c,79 ::            break;
J       L_nand_chip_select5
NOP     
;NandControl.c,81 ::            case 1:
L_nand_chip_select7:
;NandControl.c,82 ::            ctrl_nce0 = ctrl_nce2 = ctrl_nce3 = 1;
LUI     R2, BitMask(LATB14_bit+0)
ORI     R2, R2, BitMask(LATB14_bit+0)
_SX     
_LX     
EXT     R3, R2, BitPos(LATB14_bit+0), 1
_LX     
INS     R2, R3, BitPos(LATF0_bit+0), 1
_SX     
_LX     
EXT     R3, R2, BitPos(LATF0_bit+0), 1
_LX     
INS     R2, R3, BitPos(LATB8_bit+0), 1
_SX     
;NandControl.c,83 ::            ctrl_nce1 = 0;
LUI     R2, BitMask(LATF1_bit+0)
ORI     R2, R2, BitMask(LATF1_bit+0)
_SX     
;NandControl.c,84 ::            break;
J       L_nand_chip_select5
NOP     
;NandControl.c,86 ::            case 2:
L_nand_chip_select8:
;NandControl.c,87 ::            ctrl_nce0 = ctrl_nce1 = ctrl_nce3 = 1;
LUI     R2, BitMask(LATB14_bit+0)
ORI     R2, R2, BitMask(LATB14_bit+0)
_SX     
_LX     
EXT     R3, R2, BitPos(LATB14_bit+0), 1
_LX     
INS     R2, R3, BitPos(LATF1_bit+0), 1
_SX     
_LX     
EXT     R3, R2, BitPos(LATF1_bit+0), 1
_LX     
INS     R2, R3, BitPos(LATB8_bit+0), 1
_SX     
;NandControl.c,88 ::            ctrl_nce2 = 0;
LUI     R2, BitMask(LATF0_bit+0)
ORI     R2, R2, BitMask(LATF0_bit+0)
_SX     
;NandControl.c,89 ::            break;
J       L_nand_chip_select5
NOP     
;NandControl.c,91 ::            case 3:
L_nand_chip_select9:
;NandControl.c,92 ::            ctrl_nce0 = ctrl_nce1 = ctrl_nce2 = 1;
LUI     R2, BitMask(LATF0_bit+0)
ORI     R2, R2, BitMask(LATF0_bit+0)
_SX     
_LX     
EXT     R3, R2, BitPos(LATF0_bit+0), 1
_LX     
INS     R2, R3, BitPos(LATF1_bit+0), 1
_SX     
_LX     
EXT     R3, R2, BitPos(LATF1_bit+0), 1
_LX     
INS     R2, R3, BitPos(LATB8_bit+0), 1
_SX     
;NandControl.c,93 ::            ctrl_nce3 = 0;
LUI     R2, BitMask(LATB14_bit+0)
ORI     R2, R2, BitMask(LATB14_bit+0)
_SX     
;NandControl.c,94 ::            break;
J       L_nand_chip_select5
NOP     
;NandControl.c,96 ::            default:
L_nand_chip_select10:
;NandControl.c,97 ::            break;
J       L_nand_chip_select5
NOP     
;NandControl.c,98 ::            }
L_nand_chip_select4:
SEH     R2, R25
BNE     R2, R0, L__nand_chip_select35
NOP     
J       L_nand_chip_select6
NOP     
L__nand_chip_select35:
SEH     R3, R25
ORI     R2, R0, 1
BNE     R3, R2, L__nand_chip_select37
NOP     
J       L_nand_chip_select7
NOP     
L__nand_chip_select37:
SEH     R3, R25
ORI     R2, R0, 2
BNE     R3, R2, L__nand_chip_select39
NOP     
J       L_nand_chip_select8
NOP     
L__nand_chip_select39:
SEH     R3, R25
ORI     R2, R0, 3
BNE     R3, R2, L__nand_chip_select41
NOP     
J       L_nand_chip_select9
NOP     
L__nand_chip_select41:
J       L_nand_chip_select10
NOP     
L_nand_chip_select5:
;NandControl.c,99 ::            }
L_end_nand_chip_select:
JR      RA
NOP     
; end of _nand_chip_select
_nand_chip_unselect:
;NandControl.c,101 ::           void nand_chip_unselect()
;NandControl.c,103 ::           ctrl_nce0 = 1;
LUI     R2, BitMask(LATB8_bit+0)
ORI     R2, R2, BitMask(LATB8_bit+0)
_SX     
;NandControl.c,104 ::           ctrl_nce1 = 1;
LUI     R2, BitMask(LATF1_bit+0)
ORI     R2, R2, BitMask(LATF1_bit+0)
_SX     
;NandControl.c,105 ::           ctrl_nce2 = 1;
LUI     R2, BitMask(LATF0_bit+0)
ORI     R2, R2, BitMask(LATF0_bit+0)
_SX     
;NandControl.c,106 ::           ctrl_nce3 = 1;
LUI     R2, BitMask(LATB14_bit+0)
ORI     R2, R2, BitMask(LATB14_bit+0)
_SX     
;NandControl.c,107 ::           }
L_end_nand_chip_unselect:
JR      RA
NOP     
; end of _nand_chip_unselect
_nand_send_command:
;NandControl.c,110 ::           void nand_send_command(unsigned char cmd)
ADDIU   SP, SP, -4
SW      RA, 0(SP)
;NandControl.c,112 ::           data_line_write_byte(cmd);
JAL     _data_line_write_byte+0
NOP     
;NandControl.c,113 ::           ctrl_ale = 0;
LUI     R2, BitMask(LATD0_bit+0)
ORI     R2, R2, BitMask(LATD0_bit+0)
_SX     
;NandControl.c,114 ::           ctrl_nre = 1;
LUI     R2, BitMask(LATD4_bit+0)
ORI     R2, R2, BitMask(LATD4_bit+0)
_SX     
;NandControl.c,115 ::           ctrl_nwe = 0;
LUI     R2, BitMask(LATE0_bit+0)
ORI     R2, R2, BitMask(LATE0_bit+0)
_SX     
;NandControl.c,116 ::           ctrl_cle = 1;
LUI     R2, BitMask(LATB15_bit+0)
ORI     R2, R2, BitMask(LATB15_bit+0)
_SX     
;NandControl.c,117 ::           ctrl_nwe = 1;
LUI     R2, BitMask(LATE0_bit+0)
ORI     R2, R2, BitMask(LATE0_bit+0)
_SX     
;NandControl.c,118 ::           ctrl_cle = 0;
LUI     R2, BitMask(LATB15_bit+0)
ORI     R2, R2, BitMask(LATB15_bit+0)
_SX     
;NandControl.c,119 ::           }
L_end_nand_send_command:
LW      RA, 0(SP)
ADDIU   SP, SP, 4
JR      RA
NOP     
; end of _nand_send_command
_nand_send_address:
;NandControl.c,121 ::           void nand_send_address(unsigned char* addr, int len)
ADDIU   SP, SP, -16
SW      RA, 0(SP)
;NandControl.c,124 ::           ctrl_cle = 0;
SW      R25, 4(SP)
LUI     R2, BitMask(LATB15_bit+0)
ORI     R2, R2, BitMask(LATB15_bit+0)
_SX     
;NandControl.c,125 ::           ctrl_nre = 1;
LUI     R2, BitMask(LATD4_bit+0)
ORI     R2, R2, BitMask(LATD4_bit+0)
_SX     
;NandControl.c,126 ::           ctrl_ale = 1;
LUI     R2, BitMask(LATD0_bit+0)
ORI     R2, R2, BitMask(LATD0_bit+0)
_SX     
;NandControl.c,127 ::           if(0 == addr)
BEQ     R25, R0, L__nand_send_address45
NOP     
J       L_nand_send_address11
NOP     
L__nand_send_address45:
;NandControl.c,129 ::           data_line_write_byte(0);
MOVZ    R25, R0, R0
JAL     _data_line_write_byte+0
NOP     
;NandControl.c,130 ::           ctrl_nwe = 0;
LUI     R2, BitMask(LATE0_bit+0)
ORI     R2, R2, BitMask(LATE0_bit+0)
_SX     
;NandControl.c,131 ::           ctrl_nwe = 1;
LUI     R2, BitMask(LATE0_bit+0)
ORI     R2, R2, BitMask(LATE0_bit+0)
_SX     
;NandControl.c,132 ::           }
J       L_nand_send_address12
NOP     
L_nand_send_address11:
;NandControl.c,135 ::           for(i = 0; i < len; i++)
; i start address is: 16 (R4)
MOVZ    R4, R0, R0
; i end address is: 16 (R4)
L_nand_send_address13:
; i start address is: 16 (R4)
SEH     R3, R4
SEH     R2, R26
SLT     R2, R3, R2
BNE     R2, R0, L__nand_send_address46
NOP     
J       L_nand_send_address14
NOP     
L__nand_send_address46:
;NandControl.c,137 ::           data_line_write_byte(*(addr + i));
SEH     R2, R4
ADDU    R2, R25, R2
SH      R4, 8(SP)
SH      R26, 10(SP)
SW      R25, 12(SP)
LBU     R25, 0(R2)
JAL     _data_line_write_byte+0
NOP     
LW      R25, 12(SP)
LH      R26, 10(SP)
LH      R4, 8(SP)
;NandControl.c,138 ::           ctrl_nwe = 0;
LUI     R2, BitMask(LATE0_bit+0)
ORI     R2, R2, BitMask(LATE0_bit+0)
_SX     
;NandControl.c,139 ::           ctrl_nwe = 1;
LUI     R2, BitMask(LATE0_bit+0)
ORI     R2, R2, BitMask(LATE0_bit+0)
_SX     
;NandControl.c,135 ::           for(i = 0; i < len; i++)
ADDIU   R2, R4, 1
SEH     R4, R2
;NandControl.c,140 ::           }
; i end address is: 16 (R4)
J       L_nand_send_address13
NOP     
L_nand_send_address14:
;NandControl.c,141 ::           }
L_nand_send_address12:
;NandControl.c,142 ::           ctrl_ale = 0;
LUI     R2, BitMask(LATD0_bit+0)
ORI     R2, R2, BitMask(LATD0_bit+0)
_SX     
;NandControl.c,143 ::           }
L_end_nand_send_address:
LW      R25, 4(SP)
LW      RA, 0(SP)
ADDIU   SP, SP, 16
JR      RA
NOP     
; end of _nand_send_address
_nand_write:
;NandControl.c,145 ::           void nand_write(unsigned char* buffer, int len)
ADDIU   SP, SP, -12
SW      RA, 0(SP)
;NandControl.c,148 ::           ctrl_cle = 0;
LUI     R2, BitMask(LATB15_bit+0)
ORI     R2, R2, BitMask(LATB15_bit+0)
_SX     
;NandControl.c,149 ::           ctrl_ale = 0;
LUI     R2, BitMask(LATD0_bit+0)
ORI     R2, R2, BitMask(LATD0_bit+0)
_SX     
;NandControl.c,150 ::           ctrl_nre = 1;
LUI     R2, BitMask(LATD4_bit+0)
ORI     R2, R2, BitMask(LATD4_bit+0)
_SX     
;NandControl.c,151 ::           for(i = 0; i < len; i++)
; i start address is: 16 (R4)
MOVZ    R4, R0, R0
; i end address is: 16 (R4)
L_nand_write16:
; i start address is: 16 (R4)
SEH     R3, R4
SEH     R2, R26
SLT     R2, R3, R2
BNE     R2, R0, L__nand_write48
NOP     
J       L_nand_write17
NOP     
L__nand_write48:
;NandControl.c,153 ::           data_line_write_byte(*(buffer + i));
SEH     R2, R4
ADDU    R2, R25, R2
SH      R4, 4(SP)
SH      R26, 6(SP)
SW      R25, 8(SP)
LBU     R25, 0(R2)
JAL     _data_line_write_byte+0
NOP     
LW      R25, 8(SP)
LH      R26, 6(SP)
LH      R4, 4(SP)
;NandControl.c,154 ::           ctrl_nwe = 0;
LUI     R2, BitMask(LATE0_bit+0)
ORI     R2, R2, BitMask(LATE0_bit+0)
_SX     
;NandControl.c,155 ::           ctrl_nwe = 1;
LUI     R2, BitMask(LATE0_bit+0)
ORI     R2, R2, BitMask(LATE0_bit+0)
_SX     
;NandControl.c,151 ::           for(i = 0; i < len; i++)
ADDIU   R2, R4, 1
SEH     R4, R2
;NandControl.c,156 ::           }
; i end address is: 16 (R4)
J       L_nand_write16
NOP     
L_nand_write17:
;NandControl.c,157 ::           }
L_end_nand_write:
LW      RA, 0(SP)
ADDIU   SP, SP, 12
JR      RA
NOP     
; end of _nand_write
_nand_read:
;NandControl.c,159 ::           void nand_read(unsigned char* buffer, int len)
ADDIU   SP, SP, -16
SW      RA, 0(SP)
;NandControl.c,162 ::           ctrl_cle = 0;
LUI     R2, BitMask(LATB15_bit+0)
ORI     R2, R2, BitMask(LATB15_bit+0)
_SX     
;NandControl.c,163 ::           ctrl_ale = 0;
LUI     R2, BitMask(LATD0_bit+0)
ORI     R2, R2, BitMask(LATD0_bit+0)
_SX     
;NandControl.c,164 ::           ctrl_nwe = 1;
LUI     R2, BitMask(LATE0_bit+0)
ORI     R2, R2, BitMask(LATE0_bit+0)
_SX     
;NandControl.c,165 ::           for(i = 0; i < len; i++)
; i start address is: 16 (R4)
MOVZ    R4, R0, R0
; i end address is: 16 (R4)
L_nand_read19:
; i start address is: 16 (R4)
SEH     R3, R4
SEH     R2, R26
SLT     R2, R3, R2
BNE     R2, R0, L__nand_read50
NOP     
J       L_nand_read20
NOP     
L__nand_read50:
;NandControl.c,167 ::           ctrl_nre = 0;
LUI     R2, BitMask(LATD4_bit+0)
ORI     R2, R2, BitMask(LATD4_bit+0)
_SX     
; i end address is: 16 (R4)
;NandControl.c,168 ::           while(PORTD.B4 != 0);
L_nand_read22:
; i start address is: 16 (R4)
LBU     R2, Offset(PORTD+0)(GP)
EXT     R2, R2, 4, 1
BNE     R2, R0, L__nand_read52
NOP     
J       L_nand_read23
NOP     
L__nand_read52:
J       L_nand_read22
NOP     
L_nand_read23:
;NandControl.c,169 ::           *(buffer + i) = data_line_read_byte();
SEH     R2, R4
ADDU    R2, R25, R2
SW      R2, 12(SP)
SH      R4, 4(SP)
SH      R26, 6(SP)
SW      R25, 8(SP)
JAL     _data_line_read_byte+0
NOP     
LW      R25, 8(SP)
LH      R26, 6(SP)
LH      R4, 4(SP)
LW      R3, 12(SP)
SB      R2, 0(R3)
;NandControl.c,170 ::           ctrl_nre = 1;
LUI     R2, BitMask(LATD4_bit+0)
ORI     R2, R2, BitMask(LATD4_bit+0)
_SX     
; i end address is: 16 (R4)
SEH     R3, R4
;NandControl.c,171 ::           while(PORTD.B4 != 1);
L_nand_read24:
; i start address is: 12 (R3)
LBU     R2, Offset(PORTD+0)(GP)
EXT     R2, R2, 4, 1
BEQ     R2, 1, L__nand_read53
NOP     
J       L_nand_read25
NOP     
L__nand_read53:
J       L_nand_read24
NOP     
L_nand_read25:
;NandControl.c,165 ::           for(i = 0; i < len; i++)
ADDIU   R2, R3, 1
; i end address is: 12 (R3)
; i start address is: 16 (R4)
SEH     R4, R2
;NandControl.c,172 ::           }
; i end address is: 16 (R4)
J       L_nand_read19
NOP     
L_nand_read20:
;NandControl.c,173 ::           }
L_end_nand_read:
LW      RA, 0(SP)
ADDIU   SP, SP, 16
JR      RA
NOP     
; end of _nand_read
_nand_toggle_wp:
;NandControl.c,175 ::           void nand_toggle_wp()
;NandControl.c,177 ::           ctrl_nwp = ~ctrl_nwp;
_LX     
EXT     R2, R2, BitPos(LATE1_bit+0), 1
XORI    R3, R2, 1
_LX     
INS     R2, R3, BitPos(LATE1_bit+0), 1
_SX     
;NandControl.c,178 ::           Delay_us(2);
LUI     R24, 0
ORI     R24, R24, 52
L_nand_toggle_wp26:
ADDIU   R24, R24, -1
BNE     R24, R0, L_nand_toggle_wp26
NOP     
NOP     
NOP     
;NandControl.c,179 ::           }
L_end_nand_toggle_wp:
JR      RA
NOP     
; end of _nand_toggle_wp