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`ifndef BASE `define BASE vl_ `endif // default SYN_KEEP definition `define SYN_KEEP /*synthesis syn_keep = 1*/ `ifdef ACTEL `undef SYN_KEEP `define SYN_KEEP /*synthesis syn_keep = 1*/ `endif `ifdef ACTEL // ACTEL FPGA should not use logic to handle rw collision `define SYN_NO_RW_CHECK /*synthesis syn_ramstyle = "no_rw_check"*/ `else `define SYN_NO_RW_CHECK `endif `ifdef ALL `define GBUF `define SYNC_RST `define PLL `define MULTS `define MULTS18X18 `define MULT `define SHIFT_UNIT_32 `define LOGIC_UNIT `define CNT_SHREG_WRAP `define CNT_SHREG_CE_WRAP `define CNT_SHREG_CLEAR `define CNT_SHREG_CE_CLEAR `define CNT_SHREG_CE_CLEAR_WRAP `define MUX_ANDOR `define MUX2_ANDOR `define MUX3_ANDOR `define MUX4_ANDOR `define MUX5_ANDOR `define MUX6_ANDOR `define PARITY `define ROM_INIT `define RAM `define RAM_BE `define DPRAM_1R1W `define DPRAM_2R1W `define DPRAM_1R2W `define DPRAM_2R2W `define DPRAM_BE_2R2W `define FIFO_1R1W_FILL_LEVEL_SYNC `define FIFO_2R2W_SYNC_SIMPLEX `define FIFO_CMP_ASYNC `define FIFO_1R1W_ASYNC `define FIFO_2R2W_ASYNC `define FIFO_2R2W_ASYNC_SIMPLEX `define REG_FILE `define DFF `define DFF_ARRAY `define DFF_CE `define DFF_CE_CLEAR `define DF_CE_SET `define SPR `define SRP `define DFF_SR `define LATCH `define SHREG `define SHREG_CE `define DELAY `define DELAY_EMPTYFLAG `define PULSE2TOGGLE `define TOGGLE2PULSE `define SYNCHRONIZER `define CDC `define WB3AVALON_BRIDGE `define WB3WB3_BRIDGE `define WB3_ARBITER_TYPE1 `define WB_ADR_INC `define WB_RAM `define WB_SHADOW_RAM `define WB_B4_ROM `define WB_BOOT_ROM `define WB_DPRAM `define WB_CACHE `define WB_AVALON_BRIDGE `define WB_AVALON_MEM_CACHE `define IO_DFF_OE `define O_DFF `endif `ifdef PLL `ifndef SYNC_RST `define SYNC_RST `endif `endif `ifdef SYNC_RST `ifndef GBUF `define GBUF `endif `endif `ifdef WB_DPRAM `ifndef WB_ADR_INC `define WB_ADR_INC `endif `ifndef DPRAM_BE_2R2W `define DPRAM_BE_2R2W `endif `endif `ifdef WB3_ARBITER_TYPE1 `ifndef SPR `define SPR `endif `ifndef MUX_ANDOR `define MUX_ANDOR `endif `endif `ifdef WB3AVALON_BRIDGE `ifndef WB3WB3_BRIDGE `define WB3WB3_BRIDGE `endif `endif `ifdef WB3WB3_BRIDGE `ifndef CNT_SHREG_CE_CLEAR `define CNT_SHREG_CE_CLEAR `endif `ifndef DFF `define DFF `endif `ifndef DFF_CE `define DFF_CE `endif `ifndef CNT_SHREG_CE_CLEAR `define CNT_SHREG_CE_CLEAR `endif `ifndef FIFO_2R2W_ASYNC_SIMPLEX `define FIFO_2R2W_ASYNC_SIMPLEX `endif `endif `ifdef WB_AVALON_MEM_CACHE `ifndef WB_SHADOW_RAM `define WB_SHADOW_RAM `endif `ifndef WB_CACHE `define WB_CACHE `endif `ifndef WB_AVALON_BRIDGE `define WB_AVALON_BRIDGE `endif `endif `ifdef WB_CACHE `ifndef RAM `define RAM `endif `ifndef WB_ADR_INC `define WB_ADR_INC `endif `ifndef DPRAM_1R1W `define DPRAM_1R1W `endif `ifndef DPRAM_1R2W `define DPRAM_1R2W `endif `ifndef DPRAM_BE_2R2W `define DPRAM_BE_2R2W `endif `ifndef CDC `define CDC `endif `endif `ifdef WB_SHADOW_RAM `ifndef WB_RAM `define WB_RAM `endif `endif `ifdef WB_RAM `ifndef WB_ADR_INC `define WB_ADR_INC `endif `ifndef RAM_BE `define RAM_BE `endif `endif `ifdef MULTS18X18 `ifndef MULTS `define MULTS `endif `endif `ifdef SHIFT_UNIT_32 `ifndef MULTS `define MULTS `endif `endif `ifdef MUX2_ANDOR `ifndef MUX_ANDOR `define MUX_ANDOR `endif `endif `ifdef MUX3_ANDOR `ifndef MUX_ANDOR `define MUX_ANDOR `endif `endif `ifdef MUX4_ANDOR `ifndef MUX_ANDOR `define MUX_ANDOR `endif `endif `ifdef MUX5_ANDOR `ifndef MUX_ANDOR `define MUX_ANDOR `endif `endif `ifdef MUX6_ANDOR `ifndef MUX_ANDOR `define MUX_ANDOR `endif `endif `ifdef FIFO_1R1W_FILL_LEVEL_SYNC `ifndef CNT_BIN_CE `define CNT_BIN_CE `endif `ifndef DPRAM_1R1W `define DPRAM_1R1W `endif `ifndef CNT_BIN_CE_REW_Q_ZQ_L1 `define CNT_BIN_CE_REW_Q_ZQ_L1 `endif `endif `ifdef FIFO_1R1W_FILL_LEVEL_SYNC `ifndef CNT_LFSR_CE `define CNT_LFSR_CE `endif `ifndef DPRAM_2R2W `define DPRAM_2R2W `endif `ifndef CNT_BIN_CE_REW_ZQ_L1 `define CNT_BIN_CE_REW_ZQ_L1 `endif `endif `ifdef FIFO_2R2W_ASYNC_SIMPLEX `ifndef CNT_GRAY_CE_BIN `define CNT_GRAY_CE_BIN `endif `ifndef DPRAM_2R2W `define DPRAM_2R2W `endif `ifndef FIFO_CMP_ASYNC `define FIFO_CMP_ASYNC `endif `endif `ifdef FIFO_2R2W_ASYNC `ifndef FIFO_1R1W_ASYNC `define FIFO_1R1W_ASYNC `endif `endif `ifdef FIFO_1R1W_ASYNC `ifndef CNT_GRAY_CE_BIN `define CNT_GRAY_CE_BIN `endif `ifndef DPRAM_1R1W `define DPRAM_1R1W `endif `ifndef FIFO_CMP_ASYNC `define FIFO_CMP_ASYNC `endif `endif `ifdef FIFO_CMP_ASYNC `ifndef DFF_SR `define DFF_SR `endif `ifndef DFF `define DFF `endif `endif `ifdef REG_FILE `ifndef DPRAM_1R1W `define DPRAM_1R1W `endif `endif `ifdef CDC `ifndef PULSE2TOGGLE `define PULSE2TOGGLE `endif `ifndef TOGGLE2PULSE `define TOGGLE2PULSE `endif `ifndef SYNCHRONIZER `define SYNCHRONIZER `endif `endif // size to width `define SIZE2WIDTH_EXPR = (`SIZE2WIDTH==1) ? 0 : (`SIZE2WIDTH==2) ? 1 : (`SIZE2WIDTH==4) ? 2 : (`SIZE2WIDTH==8) ? 3 : (`SIZE2WIDTH==16) ? 4 : (`SIZE2WIDTH==32) ? 5 : (`SIZE2WIDTH==64) ? 6 : (`SIZE2WIDTH==128) ? 7 : 8; ////////////////////////////////////////////////////////////////////// //// //// //// Versatile library, clock and reset //// //// //// //// Description //// //// Logic related to clock and reset //// //// //// //// //// //// To Do: //// //// - add more different registers //// //// //// //// Author(s): //// //// - Michael Unneback, unneback@opencores.org //// //// ORSoC AB //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2010 Authors and OPENCORES.ORG //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// `ifdef ACTEL `ifdef GBUF `timescale 1 ns/100 ps // Global buffer // usage: // use to enable global buffers for high fan out signals such as clock and reset // Version: 8.4 8.4.0.33 module gbuf(GL,CLK); output GL; input CLK; wire GND; GND GND_1_net(.Y(GND)); CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND), .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */; endmodule `timescale 1 ns/1 ns `define MODULE gbuf module `BASE`MODULE ( i, o); `undef MODULE input i; output o; `ifdef SIM_GBUF assign o=i; `else gbuf gbuf_i0 ( .CLK(i), .GL(o)); `endif endmodule `endif `else `ifdef ALTERA `ifdef GBUF //altera `define MODULE gbuf module `BASE`MODULE ( i, o); `undef MODULE input i; output o; assign o = i; endmodule `endif `else `ifdef GBUF `timescale 1 ns/100 ps `define MODULE module `BASE`MODULE ( i, o); `undef MODULE input i; output o; assign o = i; endmodule `endif `endif // ALTERA `endif //ACTEL `ifdef SYNC_RST // sync reset // input active lo async reset, normally from external reset generator and/or switch // output active high global reset sync with two DFFs `timescale 1 ns/100 ps `define MODULE sync_rst module `BASE`MODULE ( rst_n_i, rst_o, clk); `undef MODULE input rst_n_i, clk; output rst_o; reg [1:0] tmp; always @ (posedge clk or negedge rst_n_i) if (!rst_n_i) tmp <= 2'b11; else tmp <= {1'b0,tmp[1]}; `define MODULE gbuf `BASE`MODULE buf_i0( .i(tmp[0]), .o(rst_o)); `undef MODULE endmodule `endif `ifdef PLL // vl_pll `ifdef ACTEL /////////////////////////////////////////////////////////////////////////////// `timescale 1 ps/1 ps `define MODULE pll module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o); `undef MODULE parameter index = 0; parameter number_of_clk = 1; parameter period_time_0 = 20000; parameter period_time_1 = 20000; parameter period_time_2 = 20000; parameter lock_delay = 2000000; input clk_i, rst_n_i; output lock; output reg [0:number_of_clk-1] clk_o; output [0:number_of_clk-1] rst_o; `ifdef SIM_PLL always #((period_time_0)/2) clk_o[0] <= (!rst_n_i) ? 0 : ~clk_o[0]; generate if (number_of_clk > 1) always #((period_time_1)/2) clk_o[1] <= (!rst_n_i) ? 0 : ~clk_o[1]; endgenerate generate if (number_of_clk > 2) always #((period_time_2)/2) clk_o[2] <= (!rst_n_i) ? 0 : ~clk_o[2]; endgenerate genvar i; generate for (i=0;i<number_of_clk;i=i+1) begin: clock vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i])); end endgenerate assign #lock_delay lock = rst_n_i; endmodule `else generate if (number_of_clk==1 & index==0) begin pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0])); end endgenerate // index==0 generate if (number_of_clk==1 & index==1) begin pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0])); end endgenerate // index==1 generate if (number_of_clk==1 & index==2) begin pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0])); end endgenerate // index==2 generate if (number_of_clk==1 & index==3) begin pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0])); end endgenerate // index==0 generate if (number_of_clk==2 & index==0) begin pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1])); end endgenerate // index==0 generate if (number_of_clk==2 & index==1) begin pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1])); end endgenerate // index==1 generate if (number_of_clk==2 & index==2) begin pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1])); end endgenerate // index==2 generate if (number_of_clk==2 & index==3) begin pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1])); end endgenerate // index==0 generate if (number_of_clk==3 & index==0) begin pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2])); end endgenerate // index==0 generate if (number_of_clk==3 & index==1) begin pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2])); end endgenerate // index==1 generate if (number_of_clk==3 & index==2) begin pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2])); end endgenerate // index==2 generate if (number_of_clk==3 & index==3) begin pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2])); end endgenerate // index==0 genvar i; generate for (i=0;i<number_of_clk;i=i+1) begin: clock `define MODULE sync_rst `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i])); `undef MODULE end endgenerate endmodule `endif /////////////////////////////////////////////////////////////////////////////// `else /////////////////////////////////////////////////////////////////////////////// `ifdef ALTERA `timescale 1 ps/1 ps `define MODULE pll module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o); `undef MODULE parameter index = 0; parameter number_of_clk = 1; parameter period_time_0 = 20000; parameter period_time_1 = 20000; parameter period_time_2 = 20000; parameter period_time_3 = 20000; parameter period_time_4 = 20000; parameter lock_delay = 2000000; input clk_i, rst_n_i; output lock; output reg [0:number_of_clk-1] clk_o; output [0:number_of_clk-1] rst_o; `ifdef SIM_PLL always #((period_time_0)/2) clk_o[0] <= (!rst_n_i) ? 0 : ~clk_o[0]; generate if (number_of_clk > 1) always #((period_time_1)/2) clk_o[1] <= (!rst_n_i) ? 0 : ~clk_o[1]; endgenerate generate if (number_of_clk > 2) always #((period_time_2)/2) clk_o[2] <= (!rst_n_i) ? 0 : ~clk_o[2]; endgenerate generate if (number_of_clk > 3) always #((period_time_3)/2) clk_o[3] <= (!rst_n_i) ? 0 : ~clk_o[3]; endgenerate generate if (number_of_clk > 4) always #((period_time_4)/2) clk_o[4] <= (!rst_n_i) ? 0 : ~clk_o[4]; endgenerate genvar i; generate for (i=0;i<number_of_clk;i=i+1) begin: clock vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i])); end endgenerate //assign #lock_delay lock = rst_n_i; assign lock = rst_n_i; endmodule `else `ifdef VL_PLL0 `ifdef VL_PLL0_CLK1 pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0])); `endif `ifdef VL_PLL0_CLK2 pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1])); `endif `ifdef VL_PLL0_CLK3 pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2])); `endif `ifdef VL_PLL0_CLK4 pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3])); `endif `ifdef VL_PLL0_CLK5 pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4])); `endif `endif `ifdef VL_PLL1 `ifdef VL_PLL1_CLK1 pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0])); `endif `ifdef VL_PLL1_CLK2 pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1])); `endif `ifdef VL_PLL1_CLK3 pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2])); `endif `ifdef VL_PLL1_CLK4 pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3])); `endif `ifdef VL_PLL1_CLK5 pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4])); `endif `endif `ifdef VL_PLL2 `ifdef VL_PLL2_CLK1 pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0])); `endif `ifdef VL_PLL2_CLK2 pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1])); `endif `ifdef VL_PLL2_CLK3 pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2])); `endif `ifdef VL_PLL2_CLK4 pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3])); `endif `ifdef VL_PLL2_CLK5 pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4])); `endif `endif `ifdef VL_PLL3 `ifdef VL_PLL3_CLK1 pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0])); `endif `ifdef VL_PLL3_CLK2 pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1])); `endif `ifdef VL_PLL3_CLK3 pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2])); `endif `ifdef VL_PLL3_CLK4 pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3])); `endif `ifdef VL_PLL3_CLK5 pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4])); `endif `endif genvar i; generate for (i=0;i<number_of_clk;i=i+1) begin: clock `define MODULE sync_rst `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i])); `undef MODULE end endgenerate endmodule `endif /////////////////////////////////////////////////////////////////////////////// `else // generic PLL `timescale 1 ps/1 ps `define MODULE pll module `BASE`MODULE ( clk_i, rst_n_i, lock, clk_o, rst_o); `undef MODULE parameter index = 0; parameter number_of_clk = 1; parameter period_time_0 = 20000; parameter period_time_1 = 20000; parameter period_time_2 = 20000; parameter lock_delay = 2000; input clk_i, rst_n_i; output lock; output reg [0:number_of_clk-1] clk_o; output [0:number_of_clk-1] rst_o; always #((period_time_0)/2) clk_o[0] <= (!rst_n_i) ? 0 : ~clk_o[0]; generate if (number_of_clk > 1) always #((period_time_1)/2) clk_o[1] <= (!rst_n_i) ? 0 : ~clk_o[1]; endgenerate generate if (number_of_clk > 2) always #((period_time_2)/2) clk_o[2] <= (!rst_n_i) ? 0 : ~clk_o[2]; endgenerate genvar i; generate for (i=0;i<number_of_clk;i=i+1) begin: clock `define MODULE sync_rst `BASE`MODULE rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i])); `undef MODULE end endgenerate assign #lock_delay lock = rst_n_i; endmodule `endif //altera `endif //actel `undef MODULE `endif////////////////////////////////////////////////////////////////////// //// //// //// Versatile library, registers //// //// //// //// Description //// //// Different type of registers //// //// //// //// //// //// To Do: //// //// - add more different registers //// //// //// //// Author(s): //// //// - Michael Unneback, unneback@opencores.org //// //// ORSoC AB //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2010 Authors and OPENCORES.ORG //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// `ifdef DFF `define MODULE dff module `BASE`MODULE ( d, q, clk, rst); `undef MODULE parameter width = 1; parameter reset_value = 0; input [width-1:0] d; input clk, rst