Subversion Repositories versatile_mem_ctrl

<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>TwoPortRAM_256x36</name><vendor/><library/><version/><fileSets><fileSet fileSetId="HDL_FILESET"><file fileid="0"><name>TwoPortRAM_256x36.v</name><fileType>verilogSource</fileType></file></fileSet><fileSet fileSetId="OTHER_FILESET"><file fileid="1"><name>TwoPortRAM_256x36.gen</name><userFileType>GEN</userFileType></file><file fileid="2"><name>TwoPortRAM_256x36.log</name><userFileType>LOG</userFileType></file><file fileid="3"><name>TwoPortRAM_256x36.shx</name><userFileType>Other</userFileType></file></fileSet><fileSet fileSetId="ANY_SIMULATION_FILESET"><file fileid="4"><name>TwoPortRAM_256x36_R0C0.mem</name><userFileType>MEM</userFileType></file><file fileid="5"><name>TwoPortRAM_256x36_R0C1.mem</name><userFileType>MEM</userFileType></file></fileSet></fileSets><hwModel><views><view><fileSetRef>HDL_FILESET</fileSetRef><name>HDL</name></view><view><fileSetRef>OTHER_FILESET</fileSetRef><name>OTHER</name></view><view><fileSetRef>ANY_SIMULATION_FILESET</fileSetRef><name>SIMULATION</name></view></views></hwModel><category>RAM</category><function>RAM</function><variation>Two Port RAM</variation><vendor>Actel</vendor><version>2.2</version><model><signals><signal><name>WD</name><direction>in</direction><left>35</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>RD</name><direction>out</direction><left>35</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>WEN</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>REN</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>WADDR</name><direction>in</direction><left>7</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>RADDR</name><direction>in</direction><left>7</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>WCLK</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>RCLK</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal></signals></model></Component>