Subversion Repositories versatile_mem_ctrl

 ** Message System Log
 ** Database: 
 ** Date:   Thu Jun 25 17:18:45 2009


****************
Macro Parameters
****************

Name                            : TwoPortRAM_256x36
Family                          : ProASIC3
Output Format                   : VERILOG
Type                            : RAM
Write Enable                    : Active High
Read Enable                     : Active High
Reset                           : None
LP                              : None
FF                              : None
Read Clock                      : Rising
Write Clock                     : Rising
Write Depth                     : 256
Write Width                     : 36
Read Depth                      : 256
Read Width                      : 36
RAM Type                        : Two Port
Clocks                          : Independent Read and Write Clocks
Write Mode A                    : Hold Data
Write Mode B                    : Hold Data
Read Pipeline A                 : No
Read Pipeline B                 : No
Optimized for                   : Speed
Portname DataIn                 : WD
Portname DataOut                : RD
Portname Write En               : WEN
Portname Read En                : REN
Portname WClock                 : WCLK
Portname RClock                 : RCLK
Portname WAddress               : WADDR
Portname RAddress               : RADDR
Portname Reset                  :
Portname Clock                  :
Portname DataAIn                :
Portname DataBIn                :
Portname DataAOut               :
Portname DataBOut               :
Portname AddressA               :
Portname AddressB               :
Portname CLKA                   :
Portname CLKB                   :
Portname RWA                    :
Portname RWB                    :
Portname BLKA                   :
Portname BLKB                   :
Portname LP                     :
Portname FF                     :
Initialize RAM                  : False

Cascade Configuration:
     Write Port configuration   : 256x18
     Read Port configuration    : 256x18
     Number of blocks depth wise: 1
     Number of blocks width wise: 2

**************
Compile Report
**************


Netlist Resource Report
=======================

    CORE                     Used:      2  Total:  24576   (0.01%)
    IO (W/ clocks)           Used:      0  Total:    154   (0.00%)
    Differential IO          Used:      0  Total:     35   (0.00%)
    GLOBAL (Chip+Quadrant)   Used:      0  Total:     18   (0.00%)
    PLL                      Used:      0  Total:      1   (0.00%)
    RAM/FIFO                 Used:      2  Total:     32   (6.25%)
    Low Static ICC           Used:      0  Total:      1   (0.00%)
    FlashROM                 Used:      0  Total:      1   (0.00%)
    User JTAG                Used:      0  Total:      1   (0.00%)

Wrote Verilog netlist to
L:/work/ocsvn/versatile_mem_ctrl/syn/ACTEL/vmc/smartgen\TwoPortRAM_256x36\Two\
PortRAM_256x36.v.

 ** Log Ended:   Thu Jun 25 17:18:46 2009