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<!--# set var="title" value="" --> <!--# include virtual="/ssi/ssi_start.shtml" --> <P><!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN"></P> <B><FONT FACE="Helvetica,Arial" SIZE=5 COLOR="#bf0000"><P>Project Name: VGA/LCD Controller</P> </FONT><U><FONT SIZE=4><P>Description:</B></U></FONT> </P> <P>The OpenCores VGA/LCD Controller core is a WISHBONE rev.B2 compliant embedded VGA core capable of driving CRT and LCD displays. It supports user programmable resolutions and video timings, which are limited only by the available WISHBONE bandwidth. Making it compatible with almost all available LCD and CRT displays</P> <P>The core supports a number of color modes, including 24bpp, 16bpp, 8bpp gray-scale, and 8bpp-pseudo color. The video memory and the color lookup table are located outside the primary core, thus providing the most flexible memory solution possible. They can be located on-chip or off-chip, shared with the system’s main memory (VGA on demand) or be dedicated to the VGA system. An addition to the VGA/LCD core which adds the color lookup table is available.<br> Pixel data and pseudo-color data is fetched automatically via the Wishbone master interface, making this an ideal “program-and-forget” video solution. More demanding video applications like streaming video or video games can benefit from the video-bank-switching function, which reduces flicker and cluttered images by automatically switching between video-memory pages and/or color lookup tables on each vertical retrace.<br> The core can interrupt the host on each horizontal and/or vertical synchronization pulse. The horizontal, vertical and composite synchronization polarization levels, as well as the blanking polarization level are user programmable. </P> <P><IMG SRC="block_diagram.jpg" WIDTH=722 HEIGHT=525></P> <B><U><FONT SIZE=4><P>Features:</B></U></FONT> </P> <UL> <B><LI>CRT and LCD display support</LI> <LI>Separate VSYNC/HSYNC and combined CSYNC synchronization signals</LI> <LI>Composite BLANK signal</LI> <LI>User programmable resolutions</LI> <LI>User programmable video timing</LI> <LI>24bit and 16bit color modes</LI> <LI>8bit gray-scale and 8bit pseudo-color modes</LI> <LI>Supports video memory bank switching</LI> <LI>TripleDisplay support</LI> <LI>WISHBONE Rev. B2 compliant slave and master interfaces</LI> <LI>Operates from a wide range of input clock frequencies</LI> <LI>Fully synthesizeable</LI></UL> </B><P> </P> <P>See the on-line <A HREF="http://www.opencores.org/cores/vga_lcd/vga_core.pdf">documentation</A> (current revision 0.5) for more information.</P> <P> </P> <B><U><FONT SIZE=4><P>Current Status:</B></U></FONT> </P> <UL> <LI>The core is ready and available in VHDL from OpenCores CVS via <A HREF="/cvsweb.shtml/">cvsweb</A> or via <A HREF="/cvsmodule.shtml">cvsget</A>. </LI></UL> <FONT SIZE=4><P> </P> <B><U><P>Author & Maintainer(s):</B></U></FONT> </P><DIR> <P><A HREF="mailto:rherveille@opencores.org_NOSPAM">Richard Herveille</A></P> <P> </P></DIR> <B><U><FONT SIZE=4><P>Mailing-list:</B></U></FONT> </P><DIR> <P><A HREF="mailto:cores@opencores.org_NOSPAM">cores@opencores.org_NOSPAM</A></P></DIR> <!--# include virtual="/ssi/ssi_end.shtml" -->