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[/] [vspi/] [trunk/] [projnav/] [xps/] [pcores/] [spiifc_v1_00_a/] [devl/] [projnav/] [ipcore_dir/] [buffermem_ste/] [example_design/] [buffermem_top.ucf] - Rev 14

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################################################################################
#
# (c) Copyright 2002 - 2010 Xilinx, Inc. All rights reserved.
# 
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
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# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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################################################################################

# Tx Core Period Constraint. This constraint can be modified, and is
# valid as long as it is met after place and route.
NET "CLKA"  TNM_NET     = "CLKA";
  
NET "CLKB"  TNM_NET     = "CLKB";

TIMESPEC "TS_CLKA"      = PERIOD "CLKA"  25 MHZ;
  
TIMESPEC "TS_CLKB"      = PERIOD "CLKB"  25 MHZ;

################################################################################

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