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[/] [vspi/] [trunk/] [projnav/] [xps/] [pcores/] [spiifc_v1_00_a/] [devl/] [projnav/] [ipcore_dir/] [buffermem_ste/] [example_design/] [buffermem_top.xdc] - Rev 14

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################################################################################
#
# (c) Copyright 2002 - 2011 Xilinx, Inc. All rights reserved.
# 
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
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################################################################################

# Core Period Constraint. This constraint can be modified, and is
# valid as long as it is met after place and route.
create_clock -name "TS_CLKA" -period 20.0 [ get_ports CLKA ]
  
create_clock -name "TS_CLKB" -period 20.0 [ get_ports CLKB ]
################################################################################

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