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https://opencores.org/ocsvn/vspi/vspi/trunk
Subversion Repositories vspi
[/] [vspi/] [trunk/] [projnav/] [xps/] [pcores/] [spiifc_v1_00_a/] [devl/] [projnav/] [spiloop_isim_beh1.wdb] - Rev 14
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""uu~~< w [ (K x \ )V y ] *_ z ^ +k { _ ,x | ` -e 2kspace/vSPI/src/spi_base/spiloop.v C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/spiloopmem.v C:/Xilinx/13.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V6_2.v C:/Users/mjlyons/workspace/vSPI/src/spi_base/spiifc.v C:/Xilinx/13.2/ISE_DS/ISE/verilog/src/glbl.v _top _top spiloop spiloop Reset SysClk spi_ss spi_mosi spi_clk spi_miso leds debug_out txMemAddr txMemData rcMemAddr rcMemData rcMemWE glbl glbl GSR GTS GWE PRLD p_up_tmp PLL_LOCKG PROGB_GLBL JTAG_TDO_GLBL JTAG_TCK_GLBL JTAG_TDI_GLBL JTAG_TMS_GLBL JTAG_TRST_GLBL GSR_int GTS_int PRLD_int JTAG_CAPTURE_GLBL JTAG_RESET_GLBL JTAG_SHIFT_GLBL JTAG_UPDATE_GLBL JTAG_RUNTEST_GLBL JTAG_SEL1_GLBL JTAG_SEL2_GLBL JTAG_SEL3_GLBL JTAG_SEL4_GLBL JTAG_USER_TDO1_GLBL JTAG_USER_TDO2_GLBL JTAG_USER_TDO3_GLBL JTAG_USER_TDO4_GLBL ROC_WIDTH TOC_WIDTH your_instance_name spiloopmem clka ena wea addra dina clkb enb addrb doutb mySpiIfc spiifc Reset SysClk SPI_CLK SPI_MISO SPI_MOSI SPI_SS txMemAddr txMemData rcMemAddr rcMemData rcMemWE debug_out risingSpiClk validSpiBit rcByteValid rcByte rcBitIndex packetStart SPI_CLK_reg SPI_SS_reg SPI_MOSI_reg prev_spiClk prev_spiSS state_reg rcByte_reg rcBitIndex_reg rcMemAddr_reg debug_reg txBitIndex_reg txMemAddr_reg state txBitIndex txMemAddr_oreg AddrBits Cont_65_0 spiloop inst BLK_MEM_GEN_V6_2 CLKA RSTA ENA REGCEA WEA ADDRA DINA DOUTA CLKB RSTB ENB REGCEB WEB ADDRB DINB DOUTB INJECTSBITERR INJECTDBITERR SBITERR DBITERR RDADDRECC S_ACLK S_ARESETN S_AXI_AWID S_AXI_AWADDR S_AXI_AWLEN S_AXI_AWSIZE S_AXI_AWBURST S_AXI_AWVALID S_AXI_AWREADY S_AXI_WDATA S_AXI_WSTRB S_AXI_WLAST S_AXI_WVALID S_AXI_WREADY S_AXI_BID S_AXI_BRESP S_AXI_BVALID S_AXI_BREADY S_AXI_ARID S_AXI_ARADDR S_AXI_ARLEN S_AXI_ARSIZE S_AXI_ARBURST S_AXI_ARVALID S_AXI_ARREADY S_AXI_RID S_AXI_RDATA S_AXI_RRESP S_AXI_RLAST S_AXI_RVALID S_AXI_RREADY S_AXI_INJECTSBITERR S_AXI_INJECTDBITERR S_AXI_SBITERR S_AXI_DBITERR S_AXI_RDADDRECC s_axi_awaddr_out_c s_axi_araddr_out_c s_axi_wr_en_c s_axi_rd_en_c s_aresetn_a_c s_axi_arlen_c s_axi_rid_c s_axi_rdata_c s_axi_rresp_c s_axi_rlast_c s_axi_rvalid_c s_axi_rready_c regceb_c s_axi_payload_c m_axi_payload_c injectsbiterr_in injectdbiterr_in rsta_in ena_in regcea_in wea_in addra_in dina_in C_CORENAME C_FAMILY C_XDEVICEFAMILY C_INTERFACE_TYPE C_AXI_TYPE C_AXI_SLAVE_TYPE C_HAS_AXI_ID C_AXI_ID_WIDTH C_MEM_TYPE C_BYTE_SIZE C_ALGORITHM C_PRIM_TYPE C_LOAD_INIT_FILE C_INIT_FILE_NAME C_USE_DEFAULT_DATA C_DEFAULT_DATA C_RST_TYPE C_HAS_RSTA C_RST_PRIORITY_A C_RSTRAM_A C_INITA_VAL C_HAS_ENA C_HAS_REGCEA C_USE_BYTE_WEA C_WEA_WIDTH C_WRITE_MODE_A C_WRITE_WIDTH_A C_READ_WIDTH_A C_WRITE_DEPTH_A C_READ_DEPTH_A C_ADDRA_WIDTH C_HAS_RSTB C_RST_PRIORITY_B C_RSTRAM_B C_INITB_VAL C_HAS_ENB C_HAS_REGCEB C_USE_BYTE_WEB C_WEB_WIDTH C_WRITE_MODE_B C_WRITE_WIDTH_B C_READ_WIDTH_B C_WRITE_DEPTH_B C_READ_DEPTH_B C_ADDRB_WIDTH C_HAS_MEM_OUTPUT_REGS_A C_HAS_MEM_OUTPUT_REGS_B C_HAS_MUX_OUTPUT_REGS_A C_HAS_MUX_OUTPUT_REGS_B C_HAS_SOFTECC_INPUT_REGS_A C_HAS_SOFTECC_OUTPUT_REGS_B C_MUX_PIPELINE_STAGES C_USE_SOFTECC C_USE_ECC C_HAS_INJECTERRC_SIM_COLLISION_CHECK C_COMMON_CLK C_DISABLE_WARN_BHV_COLL C_DISABLE_WARN_BHV_RANGE FLOP_DELAY C_AXI_PAYLOAD AXI_FULL_MEMORY_SLAVE C_AXI_ADDR_WIDTH_MSB C_AXI_ADDR_WIDTH LOWER_BOUND_VAL C_AXI_ADDR_WIDTH_LSB C_AXI_OS_WR log2roundup log2roundup data_value log2roundup width cnt divroundup divroundup data_value divisor divroundup div native_mem_module.blk_mem_gen_v6_2_inst BLK_MEM_GEN_V6_2_mem_module CLKA RSTA ENA REGCEA WEA ADDRA DINA DOUTA CLKB RSTB ENB REGCEB WEB ADDRB DINB DOUTB INJECTSBITERR INJECTDBITERR SBITERR DBITERR RDADDRECC sbiterr_sdp dbiterr_sdp dout_i dbiterr_i sbiterr_i rdaddrecc_i rdaddrecc_sdp ena_i enb_i reseta_i resetb_i wea_i web_i rea_i reb_i async_coll.addra_delay async_coll.wea_delay async_coll.ena_delay async_coll.addrb_delay async_coll.web_delay async_coll.enb_delay memory doublebit_error sbiterr_arr dbiterr_arr softecc_sbiterr_arr softecc_dbiterr_arr memory_out_a memory_out_b sbiterr_in dbiterr_in rdaddrecc_in inita_val initb_val is_collision is_collision_a is_collision_delay_a is_collision_b is_collision_delay_b status initfile mif_data inita_str initb_str default_data_str init_file_str cnt write_addr_a_width read_addr_a_width write_addr_b_width read_addr_b_width C_CORENAME C_FAMILY C_XDEVICEFAMILY C_MEM_TYPE C_BYTE_SIZE C_ALGORITHM C_PRIM_TYPE C_LOAD_INIT_FILE C_INIT_FILE_NAME C_USE_DEFAULT_DATA C_DEFAULT_DATA C_RST_TYPE C_HAS_RSTA C_RST_PRIORITY_A C_RSTRAM_A C_INITA_VAL C_HAS_ENA C_HAS_REGCEA C_USE_BYTE_WEA C_WEA_WIDTH C_WRITE_MODE_A C_WRITE_WIDTH_A C_READ_WIDTH_A C_WRITE_DEPTH_A C_READ_DEPTH_A C_ADDRA_WIDTH C_HAS_RSTB C_RST_PRIORITY_B C_RSTRAM_B C_INITB_VAL C_HAS_ENB C_HAS_REGCEB C_USE_BYTE_WEB C_WEB_WIDTH C_WRITE_MODE_B C_WRITE_WIDTH_B C_READ_WIDTH_B C_WRITE_DEPTH_B C_READ_DEPTH_B C_ADDRB_WIDTH C_HAS_MEM_OUTPUT_REGS_A C_HAS_MEM_OUTPUT_REGS_B C_HAS_MUX_OUTPUT_REGS_A C_HAS_MUX_OUTPUT_REGS_B C_HAS_SOFTECC_INPUT_REGS_A C_HAS_SOFTECC_OUTPUT_REGS_B C_MUX_PIPELINE_STAGES C_USE_SOFTECC C_USE_ECC C_HAS_INJECTERR C_SIM_COLLISION_CHECK C_COMMON_CLK FLOP_DELAY C_DISABLE_WARN_BHV_COLL C_DISABLE_WARN_BHV_RANGE ADDRFILE COLLFILE ERRFILE COLL_DELAY CHKBIT_WIDTH MIN_WIDTH_A MIN_WIDTH_B MIN_WIDTH MAX_DEPTH_A MAX_DEPTH_B MAX_DEPTH WRITE_WIDTH_RATIO_A READ_WIDTH_RATIO_A WRITE_WIDTH_RATIO_B READ_WIDTH_RATIO_B WRITE_ADDR_A_DIV READ_ADDR_A_DIV WRITE_ADDR_B_DIV READ_ADDR_B_DIV BYTE_SIZE C_FAMILY_LOCALPARAM SINGLE_PORT IS_ROM HAS_A_WRITE HAS_B_WRITE HAS_A_READ HAS_B_READ HAS_B_PORT MUX_PIPELINE_STAGES_A MUX_PIPELINE_STAGES_B NUM_OUTPUT_STAGES_A NUM_OUTPUT_STAGES_B Always_3888_0 BLK_MEM_GEN_V6_2 Cont_3999_1 BLK_MEM_GEN_V6_2 Cont_4000_2 BLK_MEM_GEN_V6_2 Cont_4001_3 BLK_MEM_GEN_V6_2 Cont_4002_4 BLK_MEM_GEN_V6_2 Cont_4003_5 BLK_MEM_GEN_V6_2 Cont_4004_6 BLK_MEM_GEN_V6_2 Cont_4014_7 BLK_MEM_GEN_V6_2 write_a write_a addr byte_en data inj_sbiterr inj_dbiterr current_contents address i write_b write_b addr byte_en data current_contents address i read_a read_a addr reset address i read_b read_b addr reset address i reset_a reset_a reset reset_b reset_b reset init_memory init_memory i addr_step status default_data log2roundup log2roundup data_value log2roundup width cnt collision_check collision_check addr_a iswrite_a addr_b iswrite_b collision_check c_aw_bw c_aw_br c_ar_bw scaled_addra_to_waddrb_width scaled_addrb_to_waddrb_width scaled_addra_to_waddra_width scaled_addrb_to_waddra_width scaled_addra_to_raddrb_width scaled_addrb_to_raddrb_width scaled_addra_to_raddra_width scaled_addrb_to_raddra_width reg_a BLK_MEM_GEN_V6_2_output_stage CLK RST EN REGCE DIN SBITERR_IN DBITERR_IN RDADDRECC_IN en_i regce_i rst_i DOUT SBITERR DBITERR RDADDRECC out_regs rdaddrecc_regs sbiterr_regs dbiterr_regs init_str init_val C_FAMILY C_XDEVICEFAMILY C_RST_TYPE C_HAS_RST C_RSTRAM C_RST_PRIORITY C_INIT_VAL C_HAS_EN C_HAS_REGCE C_DATA_WIDTH C_ADDRB_WIDTH C_HAS_MEM_OUTPUT_REGS C_USE_SOFTECC C_USE_ECC NUM_STAGES FLOP_DELAY REG_STAGES reg_b BLK_MEM_GEN_V6_2_output_stage CLK RST EN REGCE DIN SBITERR_IN DBITERR_IN RDADDRECC_IN en_i regce_i rst_i DOUT SBITERR DBITERR RDADDRECC out_regs rdaddrecc_regs sbiterr_regs dbiterr_regs init_str init_val C_FAMILYC_XDEVICEFAMILY C_RST_TYPE C_HAS_RST C_RSTRAM C_RST_PRIORITY C_INIT_VAL C_HAS_EN C_HAS_REGCE C_DATA_WIDTH C_ADDRB_WIDTH C_HAS_MEM_OUTPUT_REGS C_USE_SOFTECC C_USE_ECC NUM_STAGES FLOP_DELAY REG_STAGES has_softecc_output_reg_stage BLK_MEM_GEN_V6_2_softecc_output_reg_stage CLK DIN SBITERR_IN DBITERR_IN RDADDRECC_IN DOUT SBITERR DBITERR RDADDRECC dout_i sbiterr_i dbiterr_i rdaddrecc_i C_DATA_WIDTH C_ADDRB_WIDTH C_HAS_SOFTECC_OUTPUT_REGS_B C_USE_SOFTECC FLOP_DELAY Cont_2330_0 BLK_MEM_GEN_V6_2_mem_module Cont_2331_1 BLK_MEM_GEN_V6_2_mem_module Cont_2332_2 BLK_MEM_GEN_V6_2_mem_module Cont_2336_3 BLK_MEM_GEN_V6_2_mem_module Cont_2337_4 BLK_MEM_GEN_V6_2_mem_module Cont_2338_5 BLK_MEM_GEN_V6_2_mem_module Cont_2339_6 BLK_MEM_GEN_V6_2_mem_module Cont_2340_7 BLK_MEM_GEN_V6_2_mem_module Cont_2341_8 BLK_MEM_GEN_V6_2_mem_module Cont_2345_9 BLK_MEM_GEN_V6_2_mem_module Cont_2349_10 BLK_MEM_GEN_V6_2_mem_module Initial_2918_11 BLK_MEM_GEN_V6_2_mem_module Always_3225_12 BLK_MEM_GEN_V6_2_mem_module Always_3267_13 BLK_MEM_GEN_V6_2_mem_module NetDecl_3438_14 BLK_MEM_GEN_V6_2_mem_module NetDecl_3439_15 BLK_MEM_GEN_V6_2_mem_module NetDecl_3440_16 BLK_MEM_GEN_V6_2_mem_module NetDecl_3441_17 BLK_MEM_GEN_V6_2_mem_module NetDecl_3442_18 BLK_MEM_GEN_V6_2_mem_module NetDecl_3443_19 BLK_MEM_GEN_V6_2_mem_module Always_3446_20 BLK_MEM_GEN_V6_2_mem_module Always_3487_21 BLK_MEM_GEN_V6_2_mem_module Cont_1671_0 BLK_MEM_GEN_V6_2_output_stage Cont_1677_1 BLK_MEM_GEN_V6_2_output_stage Cont_1681_2 BLK_MEM_GEN_V6_2_output_stage Initial_1686_3 BLK_MEM_GEN_V6_2_output_stage Always_1705_4 BLK_MEM_GEN_V6_2_output_stage Cont_1671_0 BLK_MEM_GEN_V6_2_output_stage Cont_1677_1 BLK_MEM_GEN_V6_2_output_stage Cont_1681_2 BLK_MEM_GEN_V6_2_output_stage Initial_1686_3 BLK_MEM_GEN_V6_2_output_stage Always_1705_4 BLK_MEM_GEN_V6_2_output_stage Always_1930_0 BLK_MEM_GEN_V6_2_softecc_output_reg_stage Always_103_0 spiifc Always_123_1 spiifc Cont_126_2 spiifc Cont_127_3 spiifc Always_130_4 spiifc Cont_133_5 spiifc Always_136_6 spiifc Cont_144_7 spiifc Cont_145_8 spiifc Cont_146_9 spiifc Cont_149_10 spiifc Cont_150_11 spiifc Cont_151_12 spiifc Always_152_13 spiifc Always_163_14 spiifc Always_176_15 spiifc Cont_184_16 spiifc Cont_185_17 spiifc Always_188_18 spiifc Always_198_19 spiifc Always_217_20 spiifc Cont_222_21 spiifc NetDecl_16_0 glbl Cont_47_1 glbl Cont_48_2 glbl Cont_49_3 glbl Initial_51_4 glbl Initial_59_5 glbl