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CoreGen has not been configured with any user repositories.
CoreGen has been configured with the following Xilinx repositories:
 - '/opt/Xilinx/13.2/ISE_DS/ISE/coregen/' [using existing xil_index.xml]
INFO:encore:314 - Created non-GUI application for batch mode execution.
Wrote CGP file for project 'coregen'.
INFO:sim - Generating component instance 'icon_pro' of
   'xilinx.com:ip:chipscope_icon:1.05.a' from
   '/opt/Xilinx/13.2/ISE_DS/ISE/coregen/iprepo/Chipscope/pcores/chipscope_icon_v
   1_05_a/chipscope_icon_v1_05_a.xcd'.
Resolving generic values...
Finished resolving generic values.
Generating IP...
Gathering HDL files for icon_pro root...
Creating XST project for icon_pro...
Creating XST script file for icon_pro...
Creating XST instantiation file for icon_pro...
Running XST for icon_pro...
XST: HDL Compilation
XST: Design Hierarchy Analysis
XST: HDL Analysis
XST: HDL Synthesis
XST: Advanced HDL Synthesis
XST: Low Level Synthesis
Generating VHDL wrapper
Not generating Verilog wrapper
Creating ISE instantiation template for icon_pro...
Skipping Verilog instantiation template for icon_pro...
Finished Generation.
Generating IP instantiation template...
Generating metadata file...
Generating ISE project...
Generating README file...
Generating FLIST file...
INFO:sim - Finished FLIST file generation.
Moving files to output directory...
Finished moving files to output directory
Saved CGP file for project 'coregen'.