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https://opencores.org/ocsvn/vtach/vtach/trunk
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[/] [vtach/] [trunk/] [_xmsgs/] [pn_parser.xmsgs] - Rev 2
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<?xml version="1.0" encoding="UTF-8"?><!-- IMPORTANT: This is an internal file that has been generated --><!-- by the Xilinx ISE software. Any direct editing or --><!-- changes made to this file may result in unpredictable --><!-- behavior or data corruption. It is strongly advised that --><!-- users do not edit the contents of this file. --><!-- --><!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --><messages><msg type="info" file="ProjectMgmt" num="1769" ><arg fmt="%s" index="1">Analyzing Verilog file \"/home/alw/projects/vtachspartan/alu.v\" into library work</arg></msg><msg type="info" file="ProjectMgmt" num="1769" ><arg fmt="%s" index="1">Analyzing Verilog file \"/home/alw/projects/vtachspartan/bcdadd.v\" into library work</arg></msg><msg type="info" file="ProjectMgmt" num="1769" ><arg fmt="%s" index="1">Analyzing Verilog file \"/home/alw/projects/vtachspartan/bcdincr.v\" into library work</arg></msg><msg type="info" file="ProjectMgmt" num="1769" ><arg fmt="%s" index="1">Analyzing Verilog file \"/home/alw/projects/vtachspartan/bcdneg.v\" into library work</arg></msg><msg type="info" file="ProjectMgmt" num="1769" ><arg fmt="%s" index="1">Analyzing Verilog file \"/home/alw/projects/vtachspartan/debounce.v\" into library work</arg></msg><msg type="info" file="ProjectMgmt" num="1769" ><arg fmt="%s" index="1">Analyzing Verilog file \"/home/alw/projects/vtachspartan/digitadd.v\" into library work</arg></msg><msg type="info" file="ProjectMgmt" num="1769" ><arg fmt="%s" index="1">Analyzing Verilog file \"/home/alw/projects/vtachspartan/display.v\" into library work</arg></msg><msg type="info" file="ProjectMgmt" num="1769" ><arg fmt="%s" index="1">Analyzing Verilog file \"/home/alw/projects/vtachspartan/io_input.v\" into library work</arg></msg><msg type="info" file="ProjectMgmt" num="1769" ><arg fmt="%s" index="1">Analyzing Verilog file \"/home/alw/projects/vtachspartan/io_output.v\" into library work</arg></msg><msg type="info" file="ProjectMgmt" num="1769" ><arg fmt="%s" index="1">Analyzing Verilog file \"/home/alw/projects/vtachspartan/memory.v\" into library work</arg></msg><msg type="info" file="ProjectMgmt" num="1769" ><arg fmt="%s" index="1">Analyzing Verilog file \"/home/alw/projects/vtachspartan/usum.v\" into library work</arg></msg><msg type="info" file="ProjectMgmt" num="1769" ><arg fmt="%s" index="1">Analyzing Verilog file \"/home/alw/projects/vtachspartan/vtach.v\" into library work</arg></msg></messages>