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[/] [vtach/] [trunk/] [_xmsgs/] [xst.xmsgs] - Rev 2
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<?xml version="1.0" encoding="UTF-8"?><!-- IMPORTANT: This is an internal file that has been generatedby the Xilinx ISE software. Any direct editing orchanges made to this file may result in unpredictablebehavior or data corruption. It is strongly advised thatusers do not edit the contents of this file. --><messages><msg type="warning" file="HDLCompilers" num="259" delta="old" ><arg fmt="%s" index="1">"vtach.v" line 61 </arg>Connection to input port '<arg fmt="%s" index="2">a</arg>' does not match port size</msg><msg type="warning" file="HDLCompilers" num="261" delta="old" ><arg fmt="%s" index="1">"vtach.v" line 61 </arg>Connection to output port '<arg fmt="%s" index="2">z</arg>' does not match port size</msg><msg type="warning" file="HDLCompilers" num="259" delta="new" ><arg fmt="%s" index="1">"bcdneg.v" line 13 </arg>Connection to input port '<arg fmt="%s" index="2">a</arg>' does not match port size</msg><msg type="warning" file="HDLCompilers" num="261" delta="new" ><arg fmt="%s" index="1">"bcdneg.v" line 13 </arg>Connection to output port '<arg fmt="%s" index="2">z</arg>' does not match port size</msg><msg type="warning" file="HDLCompilers" num="259" delta="new" ><arg fmt="%s" index="1">"bcdneg.v" line 21 </arg>Connection to input port '<arg fmt="%s" index="2">a</arg>' does not match port size</msg><msg type="warning" file="HDLCompilers" num="261" delta="new" ><arg fmt="%s" index="1">"bcdneg.v" line 21 </arg>Connection to output port '<arg fmt="%s" index="2">z</arg>' does not match port size</msg><msg type="warning" file="HDLCompilers" num="259" delta="new" ><arg fmt="%s" index="1">"bcdneg.v" line 13 </arg>Connection to input port '<arg fmt="%s" index="2">a</arg>' does not match port size</msg><msg type="warning" file="HDLCompilers" num="261" delta="new" ><arg fmt="%s" index="1">"bcdneg.v" line 13 </arg>Connection to output port '<arg fmt="%s" index="2">z</arg>' does not match port size</msg><msg type="warning" file="Xst" num="2211" delta="old" >"<arg fmt="%s" index="1">ipcore_dir/mainmem.v</arg>" line <arg fmt="%d" index="2">18</arg>: Instantiating black box module <<arg fmt="%s" index="3">mainmem</arg>>.</msg><msg type="warning" file="Xst" num="1464" delta="old" >"<arg fmt="%s" index="1">io_output.v</arg>" line <arg fmt="%d" index="2">14</arg>: Exactly equal expression will be synthesized as an equal expression, simulation mismatch is possible.</msg><msg type="warning" file="Xst" num="864" delta="old" >"<arg fmt="%s" index="1">io_output.v</arg>" line <arg fmt="%d" index="2">14</arg>: Comparisons to 'X' or 'Z' are treated as always false.</msg><msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">rst</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.</msg><msg type="warning" file="Xst" num="1290" delta="new" >Hierarchical block <<arg fmt="%s" index="1">add3</arg>> is unconnected in block <<arg fmt="%s" index="2">inc</arg>>.It will be removed from the design.</msg><msg type="warning" file="Xst" num="1290" delta="new" >Hierarchical block <<arg fmt="%s" index="1">add4</arg>> is unconnected in block <<arg fmt="%s" index="2">inc</arg>>.It will be removed from the design.</msg><msg type="warning" file="Xst" num="1290" delta="new" >Hierarchical block <<arg fmt="%s" index="1">add4</arg>> is unconnected in block <<arg fmt="%s" index="2">inc</arg>>.It will be removed from the design.</msg><msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">v_8</arg>> in Unit <<arg fmt="%s" index="2">in</arg>> is equivalent to the following <arg fmt="%s" index="3">4 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><v_9> <v_10> <v_11> <v_12> </arg></msg><msg type="warning" file="Xst" num="1710" delta="old" >FF/Latch <<arg fmt="%s" index="1">v_8</arg>> (without init value) has a constant value of <arg fmt="%d" index="2">0</arg> in block <<arg fmt="%s" index="3">in</arg>>. This FF/Latch will be trimmed during the optimization process.</msg><msg type="warning" file="Xst" num="2404" delta="old" > FFs/Latches <<arg fmt="%s" index="1">v</arg><<arg fmt="%d" index="2">12</arg>:<arg fmt="%d" index="3">8</arg>>> (without init value) have a constant value of <arg fmt="%c" index="4">0</arg> in block <<arg fmt="%s" index="5">io_input</arg>>.</msg><msg type="info" file="Xst" num="1901" delta="old" >Instance <arg fmt="%s" index="1">U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram</arg> in unit <arg fmt="%s" index="2">U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_init.ram/spram.ram</arg> of type <arg fmt="%s" index="3">RAMB16_S36_S36</arg> has been replaced by <arg fmt="%s" index="4">RAMB16</arg></msg><msg type="warning" file="Xst" num="2040" delta="old" >Unit <arg fmt="%s" index="1">alu</arg>: <arg fmt="%d" index="2">13</arg> multi-source signals are replaced by logic (pull-up <arg fmt="%s" index="3">yes</arg>): </msg><msg type="warning" file="Xst" num="2042" delta="old" >Unit <arg fmt="%s" index="1">memory</arg>: <arg fmt="%d" index="2">13</arg> internal tristates are replaced by logic (pull-up <arg fmt="%s" index="3">yes</arg>): </msg><msg type="warning" file="Xst" num="2042" delta="old" >Unit <arg fmt="%s" index="1">io_input</arg>: <arg fmt="%d" index="2">13</arg> internal tristates are replaced by logic (pull-up <arg fmt="%s" index="3">yes</arg>): </msg><msg type="info" file="Xst" num="2260" delta="old" >The FF/Latch <<arg fmt="%s" index="1">dbus<2>LogicTrst18_SW0_SW0_FRB</arg>> in Unit <<arg fmt="%s" index="2">top</arg>> is equivalent to the following <arg fmt="%s" index="3">3 FFs/Latches</arg> : <arg fmt="%s" index="4"><dbus<1>LogicTrst18_SW0_SW0_FRB> <dbus<3>LogicTrst18_SW0_SW0_FRB> <dbus<1>LogicTrst181_SW0_SW0_FRB> </arg></msg><msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">dbus<2>LogicTrst18_SW0_SW0_FRB</arg>> in Unit <<arg fmt="%s" index="2">top</arg>> is equivalent to the following <arg fmt="%s" index="3">3 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><dbus<1>LogicTrst18_SW0_SW0_FRB> <dbus<3>LogicTrst18_SW0_SW0_FRB> <dbus<1>LogicTrst181_SW0_SW0_FRB> </arg></msg></messages>