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--
-- BLK MEM GEN v6.2 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
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-- possibility of the same.
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-- CRITICAL APPLICATIONS
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--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
 
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--
-- Filename: bmg_wrapper.vhd
--
-- Description:
--   This is the actual BMG core wrapper.
--
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-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
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--
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-- Library Declarations
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
 
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
 
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-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY mainmem_top IS
  PORT (
      --Inputs - Port A
 
    WEA            : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    ADDRA          : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
 
    DINA           : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
 
    DOUTA          : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
    CLKA       : IN STD_LOGIC
 
 
  );
 
END mainmem_top;
 
 
ARCHITECTURE xilinx OF mainmem_top IS
 
  COMPONENT BUFG IS
  PORT (
     I      : IN STD_ULOGIC;
     O      : OUT STD_ULOGIC
  );
  END COMPONENT;
 
  COMPONENT mainmem IS
  PORT (
      --Port A
 
    WEA        : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    ADDRA      : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
 
    DINA       : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
 
    DOUTA      : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
 
    CLKA       : IN STD_LOGIC
 
 
 
  );
  END COMPONENT;
 
  SIGNAL CLKA_buf     : STD_LOGIC;
  SIGNAL CLKB_buf     : STD_LOGIC;
  SIGNAL S_ACLK_buf   : STD_LOGIC;
 
BEGIN
 
  bufg_A : BUFG
    PORT MAP (
     I => CLKA,
     O => CLKA_buf
     );
 
 
 
  bmg0 : mainmem
    PORT MAP (
      --Port A
 
      WEA        => WEA,
      ADDRA      => ADDRA,
 
      DINA       => DINA,
 
      DOUTA      => DOUTA,
 
      CLKA       => CLKA_buf
 
 
    );
 
END xilinx;