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Release 13.2 par O.61xd (lin64)
Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.

enterprise::  Sat May 25 07:43:38 2013

par -filter iseconfig/filter.filter -w -intstyle ise -pl high -rl high -xe n -t
1 top_map.ncd top.ncd top.pcf 


Constraints file: top.pcf.
Loading device for application Rf_Device from file '3s1000.nph' in environment /opt/Xilinx/13.2/ISE_DS/ISE/.
   "top" is an NCD, version 3.2, device xc3s1000, package ft256, speed -4
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:54 - 'xc3s1000' is a WebPack part.
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue
to function, but you no longer qualify for Xilinx software updates or new releases.

----------------------------------------------------------------------

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)


Device speed data version:  "PRODUCTION 1.39 2011-06-20".



Device Utilization Summary:

   Number of BUFGMUXs                        3 out of 8      37%
   Number of DCMs                            1 out of 4      25%
   Number of External IOBs                  32 out of 173    18%
      Number of LOCed IOBs                  32 out of 32    100%

   Number of RAMB16s                         1 out of 24      4%
   Number of Slices                        347 out of 7680    4%
      Number of SLICEMs                      0 out of 3840    0%



Overall effort level (-ol):   Not applicable because -pl and -rl switches are used
Router effort level (-rl):    High 

Starting initial Timing Analysis.  REAL time: 3 secs 
Finished initial Timing Analysis.  REAL time: 3 secs 

Starting Router


Phase  1  : 2570 unrouted;      REAL time: 3 secs 

Phase  2  : 2338 unrouted;      REAL time: 3 secs 

Phase  3  : 500 unrouted;      REAL time: 3 secs 

Phase  4  : 500 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 4 secs 

Phase  5  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 4 secs 

Updating file: top.ncd with current fully routed design.

Phase  6  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 4 secs 

Phase  7  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 4 secs 

Phase  8  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 4 secs 

Total REAL time to Router completion: 4 secs 
Total CPU time to Router completion: 4 secs 

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|              clkdiv |      BUFGMUX4| No   |  177 |  0.380     |  1.131      |
+---------------------+--------------+------+------+------------+-------------+
|               clkls |      BUFGMUX0| No   |    3 |  0.014     |  0.846      |
+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.

* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.

Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)

Number of Timing Constraints that were not applied: 1

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

----------------------------------------------------------------------------------------------------------
  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing   
                                            |             |    Slack   | Achievable | Errors |    Score   
----------------------------------------------------------------------------------------------------------
  TS_clk = PERIOD TIMEGRP "clk" 50 MHz HIGH | MINLOWPULSE |    14.000ns|     6.000ns|       0|           0
   50%                                      |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_clockdll_CLKFX_BUF = PERIOD TIMEGRP "c | SETUP       |    23.477ns|     7.773ns|       0|           0
  lockdll_CLKFX_BUF" TS_clk * 0.64 HIGH     | HOLD        |     1.282ns|            |       0|           0
       50%                                  |             |            |            |        |            
----------------------------------------------------------------------------------------------------------


Derived Constraint Report
Review Timing Report for more details on the following derived constraints.
To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
or "Run Timing Analysis" from Timing Analyzer (timingan).
Derived Constraints for TS_clk
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_clk                         |     20.000ns|      6.000ns|      4.975ns|            0|            0|            0|           14|
| TS_clockdll_CLKFX_BUF         |     31.250ns|      7.773ns|          N/A|            0|            0|           14|            0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

All constraints were met.


Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 4 secs 
Total CPU time to PAR completion: 4 secs 

Peak Memory Usage:  336 MB

Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 0

Writing design to file top.ncd



PAR done!