Subversion Repositories wb2axi4

//Author     : Alex Zhang (cgzhangwei@gmail.com)
//Date       : March.05.2015
//Description: Wishbone B3 protocol interface
//             TGC : {AWPROT,AWCACHE, AWLOCK} | {ARPROT, ARCACHE,ARLOCK}
//             TGD : WID,
//             TGA : AWID| ARID,
interface wishbone_if #(
  WB_ADR_WIDTH = 32,
  WB_BTE_WIDTH = 2 , 
  WB_CIT_WIDTH = 3 ,
  WB_DAT_WIDTH = 32,
  WB_TGA_WIDTH = 8,
  WB_TGD_WIDTH = 8,
  WB_TGC_WIDTH = 4,
  WB_SEL_WIDTH = 4 

);
logic [WB_DAT_WIDTH -1 : 0] DAT_I;
logic [WB_DAT_WIDTH -1 : 0] DAT_O;
logic [WB_TGD_WIDTH -1 : 0] TGD_I;
logic [WB_TGD_WIDTH -1 : 0] TGD_O;
logic                       ACK_I;
logic [WB_ADR_WIDTH -1 : 0] ADR_O;
logic                       CYC_O;
logic                       ERR_I;
logic                       LOCK_O;
logic                       RTY_I;
logic [WB_SEL_WIDTH -1 : 0] SEL_O;
logic                       STB_O;
logic [WB_TGA_WIDTH -1 :0 ] TGA_O;
logic [WB_TGA_WIDTH -1 :0 ] TGC_O;
logic                       WE_O;
logic [WB_BTE_WIDTH -1 :0 ] BTE_O;
logic [WB_BTE_WIDTH -1 :0 ] BTE_I;
logic [WB_CTI_WIDTH -1 :0 ] CTI_O;
logic [WB_CTI_WIDTH -1 :0 ] CTI_I;


logic                       ACK_O;
logic [WB_ADR_WIDTH -1 : 0] ADR_I;
logic                       CYC_I;
logic                       ERR_O;
logic                       LOCK_I;
logic                       RTY_O;
logic [WB_SEL_WIDTH -1 : 0] SEL_I;
logic [WB_TGA_WIDTH -1 :0 ] TGA_I;
logic [WB_TGA_WIDTH -1 :0 ] TGC_I;
logic                       WE_I;

modport  master(
output ADR_O,
output TGA_O,
input  DAT_I,
input  TGD_I,
output DAT_O,
output TGD_O,
output WE_O,
output SEL_O,
output STB_O,
input  ACK_I,
output CYC_O,
input  ERR_I,
output LOCK_O,
output BTE_O,
input  RTY_I,
output TGC_O
);

modport  slave(
output ADR_I,
output TGA_I,
input  DAT_I,
input  TGD_I,
output DAT_O,
output TGD_O,
output WE_I,
output SEL_I,
output STB_I,
input  ACK_O,
output CYC_I,
input  ERR_O,
output LOCK_I,
input  BTE_I,
input  RTY_O,
output TGC_I
);


endinterface