Subversion Repositories wb_lpc

PK

__OBJSTORE__/PK
__OBJSTORE__/Autonym/PK
 __OBJSTORE__/HierarchicalDesign/PK
*__OBJSTORE__/HierarchicalDesign/HDProject/PK
__OBJSTORE__/ISimPlugin/PK
(__OBJSTORE__/ISimPlugin/SignalOrdering1/PK

       
PK

PK

 !"#$%&PK
master_bench/clk_i/wb_lpc_master_bench/wbs_adr_i/wb_lpc_master_bench/wbs_dat_i/wb_lpc_master_bench/wbs_cyc_i/wb_lpc_master_bench/wbs_sel_i/wb_lpc_master_bench/dma_chan_i/wb_lpc_master_bench/wbs_tga_i/wb_lpc_master_bench/nrst_i/wb_lpc_master_bench/dma_tc_iPK

PK
/UUT_Serirq_Host/statePK

PK
/j\e--J__OBJSTORE__/ISimPlugin/SignalOrdering1/wb_serirq_host_isim_beh.exe_StrTbl/wb_serirq_host/clk_i/wb_serirq_host/nrst_i/wb_serirq_host/wbs_adr_i/wb_serirq_host/wbs_dat_o/wb_serirq_host/wbs_dat_i/wb_serirq_host/wbs_sel_i/wb_serirq_host/wbs_tga_i/wb_serirq_host/wbs_we_i/wb_serirq_host/wbs_stb_i/wb_serirq_host/wbs_cyc_i/wb_serirq_host/wbs_ack_o/wb_serirq_host/irq_o/wb_serirq_host/serirq_o/wb_serirq_host/serirq_i/wb_serirq_host/serirq_oe/wb_serirq_host/wbs_acc/wb_serirq_host/wbs_wr/wb_serirq_host/start_cnt/wb_serirq_host/stop_cnt/wb_serirq_host/irq_cnt/wb_serirq_host/state/wb_serirq_host/lpc_dat_iPK

       
PK
__OBJSTORE__/PnAutoRun/PK
__OBJSTORE__/PnAutoRun/Scripts/PK
namespace eval Dpm {
proc GetIseVersion {} {
   set fsetName "fileset.txt"
   set fsetPath ""
   # Find the file in the Xilinx environment.
   # First, construct the environment path.
   set sep ":"; # Default to UNIX style seperator.
   if {[string compare -length 7 $::tcl_platform(platform) "windows"] == 0} {
      set sep ";"; # Platform is a Windows variant, so use semi-colon.
   }
   set xilinxPath $::env(XILINX)
   if [info exists ::env(MYXILINX)] then {
      set xilinxPath [join [list $::env(MYXILINX) $xilinxPath] $sep]
   }
   # Now look in each path of the path until we find a match.
   foreach xilElem [split $xilinxPath $sep] {
      set checkPath ${xilElem}/$fsetName
      set checkPath [ string map { \\ / } $checkPath ]
      if { [file exists $checkPath] } {
         set fsetPath $checkPath
         break
      }
   }
   if { [string equal $fsetPath ""] } {
      puts "ERROR: Can not determine the ISE software version."
      return ""
   }
   if { [catch { open $fsetPath r } fset] } {
      puts "ERROR: Could not open $fsetPath: $fset"
      return ""
   }
   # have the file open, scan for the version entry.
   set sVersion ""
   while { ![eof $fset] } {
      set line [gets $fset]
      regexp {version=(.*)} $line match sVersion
         # The above doesn't stop looking in the file. This assumes that if
         # there are multiple version entries, the last one is the one we want.
   }
   close $fset
   return $sVersion
}
proc CheckForIron {project_name} {
   
   # Determine if the currently running version of ProjNav is earlier than Jade.
   set version [GetIseVersion]
   set dotLocation [string first "." $version]
   set versionBase [string range $version 0 [expr {$dotLocation - 1}]]
   if {$versionBase < 9} {
      
      # The project file is newer than Iron, so take action to prevent the
      # file from being corrupted.
      # Make the file read-only.
      if {[string compare -length 7 $::tcl_platform(platform) "windows"]} {
         # The above will return 0 for a match to "windows" or "windows64".
         # This is the non-zero part of the if, for lin and sol.
         # Change the permissions to turn off writability.
         file attributes $project_name -permissions a-w
      } else {
         # On Windows, set file to read-only.
         file attributes $project_name -readonly 1
      }      
      
      # And tell the user about it.
      set messageText "WARNING: This project was last saved with a newer version of Project Navigator.\nThe project file will be made read-only so that it will not be invalidated by this version."
      # In the console window
      puts $messageText
      # And with a GUI message box if possible.
      ::xilinx::Dpm::TOE::loadGuiLibraries
      set iInterface 0
      set messageDisplay 0
      if {[catch {
         set iInterface [Xilinx::CitP::GetInstance $::xilinx::GuiI::IMessageDlgID]
         set messageDisplay [$iInterface GetInterface $::xilinx::GuiI::IMessageDlgID]
         if {$messageDisplay != 0} {
            # Managed to get a component to display a dialog, so use it
            set messageTitle "Incompatible Project Version (Newer)"
            set messageType 2
               # 2 corresponds to a warning dialog. TclWrapGuiI_Init.cpp doesn't put the enum into Tcl.
            set messageTimeout 300000
               # in milliseconds, 5 minutes
            set messageReturn [$messageDisplay MessageDlg $messageTitle $messageText $messageType 1 1 $messageTimeout "OK" "" ""]
         }
      } catchResult]} {
         # There was an error, probably because we aren't in a GUI enviroment.
      } else {
         # All is well.
      }
      set messageDisplay 0
      set iInterface 0
   }
      
   return 1
}
}
}
::xilinx::Dpm::CheckForIronPK
__OBJSTORE__/ProjectNavigator/PK
/__OBJSTORE__/ProjectNavigator/dpm_project_main/PK

=__OBJSTORE__/ProjectNavigator/dpm_project_main/NameMap_StrTblPK


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LUGIN_General|1204933054|FILE_ISIM_MISC|Generic||isim.hdlsourcefilesisim.hdlsourcefilesDESUT_ISIM_MISC|File||C:/hharte/work/HarteTec/cores/wb_lpc/sim/serirq_sim/isimwavedata.xwv|PLUGIN_General|1204933075|FILE_XWV|Generic||isimwavedata.xwvisimwavedata.xwvDESUT_XWV|File||C:/hharte/work/HarteTec/cores/wb_lpc/sim/serirq_sim/isim.cmd|PLUGIN_General|1216686627|FILE_CMD|Generic||isim.cmdisim.cmdDESUT_CMD|File||C:/hharte/work/HarteTec/cores/wb_lpc/sim/serirq_sim/fuse.log|PLUGIN_General|1216686627|FILE_LOG|Generic||fuse.logfuse.logDESUT_LOG|File||C:/hharte/work/HarteTec/cores/wb_lpc/sim/serirq_sim/isim|PLUGIN_General|1216686626||Generic||isimisim|File||C:/hharte/work/HarteTec/cores/wb_lpc/sim/serirq_sim/serirq_host_bench_isim_beh.exe|PLUGIN_General|1216686627|FILE_ISIM_EXE|Generic||serirq_host_bench_isim_beh.exeserirq_host_bench_isim_beh.exeDESUT_ISIM_EXE|File||C:/hharte/work/HarteTec/cores/wb_lpc/sim/serirq_sim/xilinxsim.ini|PLUGIN_General|1216686625|FILE_INI|Generic||xilinxsim.inixilinxsim.iniDESUT_INI|File||C:/hharte/work/HarteTec/cores/wb_lpc/sim/serirq_sim/serirq_host_bench_beh.prj|PLUGIN_General|1216686625|FILE_XST_PROJECT|Generic||serirq_host_bench_beh.prjserirq_host_bench_beh.prjDESUT_XST_PROJECT|File||C:/hharte/work/HarteTec/cores/wb_lpc/sim/serirq_sim/tb_serirq_top.v|PLUGIN_Verilog|1204933033|FILE_VERILOG|ComponentInstantiation||serirq_host_bench|serirq_host_bench|UUT_Serirq_Host|serirq_host||ComponentInstantiation||serirq_host_bench|serirq_host_bench|UUT_Serirq_Slave|serirq_slave||Module||serirq_host_benchserirq_host_benchDESUT_VERILOGUUT_Serirq_Slaveserirq_slaveUUT_Serirq_Hostserirq_host|File||C:/hharte/work/HarteTec/cores/wb_lpc/rtl/verilog/serirq_slave.v|PLUGIN_Verilog|1205158093||Module||serirq_slave|File||C:/hharte/work/HarteTec/cores/wb_lpc/rtl/verilog/serirq_host.v|PLUGIN_Verilog|1205158093||Module||serirq_host|File||C:/hharte/work/HarteTec/cores/wb_lpc/rtl/verilog/serirq_defines.v|PLUGIN_Verilog|1205158093|AutoGeneratedViewVIEW_AssignPackagePinsTBIND_XSTAssignPackagePinsTRAN_assignPackagePinsVIEW_XSTPreSynthesisTBINDEXT_XSTPreSynthesisToStructural_spartan3TRAN_SubProjectPreToStructuralProxyTRAN_compileBCD2TRANEXT_xstsynthesize_spartan3VIEW_StructuralTBIND_StructuralToPost-SynthesisAbstractSimulationTRAN_postSynthesisSimModelVIEW_Post-SynthesisAbstractSimulation/serirq_host_benchTBINDEXT_StructuralToTranslation_FPGATRANEXT_ngdbuild_FPGAVIEW_TranslationTBIND_xlateFloorPlannerTRAN_xlateFloorPlannerVIEW_Post-TranslateFloorPlannerTBIND_xlateAssignPackagePinsTRAN_xlateAssignPackagePinsVIEW_Post-TranslateAssignPinsTBIND_TranslationToPost-TranslateFormalityNetlistTRAN_postXlateFormalityNetlistVIEW_Post-TranslateFormalityNetlistTBIND_TranslationToPost-TranslateAbstractSimulationTRAN_postXlateSimModelVIEW_Post-TranslateAbstractSimulationTBIND_Post-TranslateAbstractToTBWPreSimulationTRAN_createPostXlateTestBenchTRAN_copyPost-TranslateAbstractToPreSimulationVIEW_TBWPost-TranslatePreSimulationTBIND_Post-TranslateAbstractToPreSimulationVIEW_Post-TranslatePreSimulationTBIND_TranslateToSmartTRAN_CopySmartXplorerResultTRAN_SmartXplorerVIEW_SmartXplorerTBIND_NGCAssignPackagePinsTRAN_ngcAssignPackagePinsVIEW_ngcAssignPackagePinsTBIND_FloorplanDesignTRAN_floorplanDesignVIEW_Post-TranslateFloorplanDesignTBIND_CreateTimingConstraintsTRAN_createTimingConstraintsVIEW_Post-TranslateTimingConstraintsTBIND_CreateAreaConstraintsTRAN_createAreaConstraintsVIEW_Post-TranslateAreaConstraintsTBINDEXT_TranslationToMap_spartan3TRANEXT_map_spartan3VIEW_MapTBIND_preRouteTrceTRAN_preRouteTrceVIEW_Post-MapStaticTimingTBIND_mapFpgaEditorTRAN_mapFpgaEditorVIEW_Post-MapFpgaEditorTBIND_mapFloorPlannerTRAN_mapFloorPlannerVIEW_Post-MapFloorPlannerTBIND_MapToPost-MapAbstractSimulationTRAN_postMapSimModelVIEW_Post-MapAbstractSimulationTBIND_Post-MapAbstractToTBWPreSimulationTRAN_createPostMapTestBenchTRAN_copyPost-MapAbstractToPreSimulationVIEW_TBWPost-MapPreSimulationTBIND_Post-MapAbstractToPreSimulationVIEW_Post-MapPreSimulationTBINDEXT_MapToPar_spartan3TRANEXT_par_spartan3VIEW_ParTBIND_postRouteTrceTRAN_postRouteTrceVIEW_Post-ParStaticTimingTBIND_postParPrimetimeNetlistTRAN_postParPrimetimeNetlistVIEW_PrimetimeNetlistTBIND_parFpgaEditorTRAN_parFpgaEditorVIEW_Post-ParFpgaEditorTBIND_parFloorPlannerTRAN_parFloorPlannerVIEW_Post-ParFloorPlannerTBIND_genPowerDataTRAN_genPowerDataVIEW_FPGAGeneratePowerDataTBIND_createIBISModelTRAN_createIBISModelVIEW_IBISModelTBIND_XpowerTRAN_XPowerVIEW_FPGAAnalyzePowerTBIND_ParToPost-ParFormalityNetlistTRAN_postParFormalityNetlistVIEW_Post-ParFormalityNetlistTBIND_ParToPost-ParClockRegionTRAN_clkRegionRptVIEW_Post-ParClockRegionReportTBIND_ParToPost-ParAsyncDelayTRAN_asynDlyRptVIEW_Post-ParAsyncDelayReportTBIND_ParToPost-ParAbstractSimulationTRAN_postParSimModelVIEW_Post-ParAbstractSimulationTBIND_Post-ParAbstractToTBWPreSimulationTRAN_createPostParTestBenchTRAN_copyPost-ParAbstractToPreSimulationVIEW_TBWPost-ParPreSimulationTBIND_TBWPost-ParPreToFuseTRAN_ISimulatePostPlace&RouteModelRunFuse(bencher)VIEW_TBWPost-ParFuseTBIND_TBWPost-ParFuseToSimulationISimTRAN_ISimulatePostPlace&RouteModel(bencher)VIEW_TBWPost-ParSimulationISimTBIND_Post-ParAbstractToPreSimulationVIEW_Post-ParPreSimulationTBIND_Post-ParPreToFuseTRAN_ISimulatePostPlace&RouteModelRunFuseVIEW_Post-ParFuseTBIND_Post-ParFuseToSimulationISimTRAN_ISimulatePostPlace&RouteModelVIEW_Post-ParSimulationISimTBIND_ParToMpprResultTRAN_copyMpprRsltVIEW_MpprResultTBIND_ParToLockedPinConstraintsTRAN_genLockedPinConstraintsVIEW_LockedPinConstraintsTBIND_ParToBackAnnoPinLocationsTRAN_backAnnoPinLocationsVIEW_BackAnnoPinLocationsTBINDEXT_ParToFPGAConfiguration_spartan3TRANEXT_bitFile_spartan3VIEW_FPGAConfigurationTBIND_analyzeDesignUsingChipscopeTRAN_analyzeDesignUsingChipscopeVIEW_AnalyzedDesignTBIND_UpdateBitstreamXPSTRAN_xpsUpdBitstreamVIEW_UpdatedBitstreamTBIND_FPGAConfigurationToFPGAGeneratePROMTRAN_genImpactFileVIEW_FPGAGeneratePROMTBIND_FPGAConfigurationToFPGAConfigureTargetDeviceTRAN_configureTargetDeviceVIEW_FPGAConfigureTargetDeviceTBIND_FPGAConfigurationToFPGAConfigureDeviceTRAN_impactProgrammingToolVIEW_FPGAConfigureDeviceTBIND_XSTAbstractToPreSynthesisTRAN_SubProjectAbstractToPreProxyTRAN_convertToHdlTRAN_copyAbstractToPreSynthesisForSynthesisVIEW_XSTAbstractSynthesis/serirq_hostTBIND_InitialToXSTAbstractSynthesisTRAN_copyInitialToXSTAbstractSynthesisVIEW_InitialTBIND_InitialToAbstractSimulationTRAN_copyInitialToAbstractSimulationVIEW_AbstractSimulationTBIND_AbstractToPostAbstractSimulationTRAN_copyAbstractToPostAbstractSimulationVIEW_PostAbstractSimulationTBIND_PostAbstractToTBWPreSimulationTRAN_viewBehavioralTestbenchTRAN_copyPostAbstractToPreSimulationVIEW_TBWPreSimulationTBIND_TBWPreToBehavioralFuseTRAN_ISimulateBehavioralModelRunFuse(bencher)VIEW_TBWBehavioralFuseTBIND_TBWBehavioralFuseToSimulationISimTRAN_ISimulateBehavioralModel(bencher)VIEW_TBWBehavioralSimulationISimTBIND_PostAbstractToPreSimulationVIEW_PreSimulationTBIND_PreToBehavioralFusefalsetrueModule|serirq_host_benchHDLXST (VHDL/Verilog)TRAN_ISimulateBehavioralModelRunFuseVIEW_BehavioralFuseTBIND_BehavioralFuseToSimulationISim1000 nsTRAN_ISimulateBehavioralModelVIEW_BehavioralSimulationISimTBIND_PostAbstractToAnnotatedPreSimulationTRAN_viewBehavioralTestbenchForAnnoTRAN_copyPostAbstractToAnnotatedPreSimulationVIEW_AnnotatedPreSimulationTBIND_PreToGenerateAnnotatedResultsFuseTRAN_ISimGenerateAnnotatedResultsRunFuseTRAN_copyPreToGenerateAnnotatedResultsFuseForTBWVIEW_AnnotatedResultsFuseTBIND_FuseToAnnotatedResultsISimTRAN_ISimGenerateAnnotatedResultsTRAN_copyFuseToAnnotatedResultsISimForTBWVIEW_AnnotatedResultsISimTBIND_AnnotatedToGenerateExpectedSimulationResultsISimTRAN_ISimGenerateExpectedSimulationResultsVIEW_ExpectedSimulationResultsISimTBINDEXT_InitialToCommon_FPGATRANEXT_compLibraries_FPGAVIEW_CommonDESPF_TRADITIONALPROP_PreferredLanguageVerilogPROP_SimulatorModelsim-SE MixedISE Simulator (VHDL/Verilog)Other MixedOther VerilogOther VHDLVCS-MXi MixedVCS-MXi VerilogVCS-MXi VHDLVCS-MX MixedVCS-MX VerilogVCS-MX VHDLNC-Sim MixedNC-Sim VerilogNC-Sim VHDLModelsim-XE VerilogModelsim-XE VHDLModelsim-PE MixedModelsim-PE VerilogModelsim-PE VHDLModelsim-SE VerilogModelsim-SE VHDLPROP_Synthesis_ToolPROP_Top_Level_Module_TypeVHDLPROP_DevSpeed-5-4PROP_DevPackagepq208fg456PROP_DevDevicexc3s50xc3s400xc3s1500lxc3s1500xc3s1000lxc3s1000xc3s200tq144ft256fg320PROP_ParSmartGuideFileNameserirq_host_guide.ncdPROP_UseSmartGuidePROP_SynthTopModule|serirq_hostNCD files (*.ncd)|*.ncdPROP_MapSmartGuideFileNamePROP_ISimSpecifySearchDirPROP_xstVeriIncludeDirPROP_PostSynthesisSimModelNameserirq_host_synthesis.vPROP_SimModelTargetPROP_ISimSpecifyDefMacroAndValuePROP_ISimSpecifySearchDirectoryPROP_ISimValueRangeCheckPROP_ISimCompileForHdlDebugPROP_ISimIncreCompilationPROP_tbwPostParTestbenchNameserirq_host_bench.timesim_tfwPROP_tbwTestbenchTargetLangPROP_PostParSimTopPROP_tbwPostMapTestbenchNameserirq_host_bench.map_tfwPROP_PostMapSimTopPROP_tbwPostXlateTestbenchNameserirq_host_bench.translate_tfwPROP_PostXlateSimTopPROP_PostParSimModelNameserirq_host_timesim.vPROP_PostMapSimModelNameserirq_host_map.vPROP_PostXlateSimModelNameserirq_host_translate.vPROP_TopDesignUnitPROPEXT_xilxBitgCfg_DCIUpdateMode_spartan3As RequiredPROPEXT_xilxBitgCfg_Rate_spartan3Default (6)PROPEXT_xilxSynthAddBufg_spartan3PROPEXT_xilxSynthMaxFanout_virtex2PROPEXT_SynthMultStyle_virtex2AutoPROPEXT_xilxMapGenInputK_virtex24PROP_MapRegDuplicationPROP_xilxMapTimingDrivenPackingPROP_MapLogicOptimizationPROP_MapPlacerCostTablePROP_MapExtraEffortNonePROP_MapEffortLevelMediumHighStandardContinue on ImpossibleNormalPROP_xilxBitgStart_Clk_MatchCyclePROP_xilxBitgCfg_DCMShutdownPROP_xilxBitgCfg_GenOpt_EnableCRCPROP_xilxBitgCfg_GenOpt_IEEE1532FilePROP_MapPowerActivityFilePROP_MapPowerReductionSAIF Files (*.saif)|*.saifVCD files (*.vcd)|*.vcdPROP_parSmartGuideFileNamePROP_mapSmartGuideFileNamePROP_xstUseSyncResetYesPROP_xstUseSyncSetPROP_xstUseClockEnablePROP_xilxSynthRegDuplicationPROP_xstOptimizeInsPrimtivesPROP_xstSlicePackingPROP_xstPackIORegisterPROP_xstMoveLastFfStagePROP_xilxSynthRegBalancingNoPROP_xstMoveFirstFfStagePROP_SynthLogicalShifterExtractPROP_SynthShiftRegExtractPROP_SynthEncoderExtractPROP_SynthDecoderExtractPROP_SynthMuxStylePROP_SynthExtractMuxMUXCYMUXFPROP_xstROMStylePROP_SynthExtractROMBlockDistributedPROP_SynthRAMStylePROP_SynthExtractRAMPROP_xstFsmStyleLUTPROP_xstCrossClockAnalysisPROP_xstSliceUtilRatioPROP_xstWriteTimingConstraintsPROP_xstCoresSearchDirPROP_xstReadCoresPROP_xstAsynToSyncPROP_xstBRAMUtilRatioPROP_xstAutoBRAMPackingPROP_xilxSynthGlobOptAllClockNetsPROP_CompxlibXlnxCoreLibPROP_impactConfigFileNamePROP_ImpactProjectFilePROP_AceActiveNamePROP_AutoGenFilePROP_primeTopLevelModulePROP_primeCorrelateOutputPROP_primeFlatternOutputNetlistPROP_primetimeBlockRamDataPROP_PreTrceTSIFilePROP_xilxPostTrceTSIFilePROP_PostTrceGenDatasheetPROP_PostTrceGenTimegroupsPROP_PreTrceGenDatasheetPROP_PreTrceGenTimegroupsPROP_xilxPostTrceStampPROP_PostTrceFastPathPROP_xilxPostTrceEndpointPathPROP_xilxPostTrceUncovPathPROP_xilxPostTrceSpeedAbsolute MinPROP_xilxPostTrceAdvAnaPROP_xilxPostTrceRptLimitPROP_xilxPostTrceRptError ReportPROP_PreTrceFastPathPROP_xilxPreTrceEndpointPathPROP_xilxPreTrceUncovPathPROP_xilxPreTrceSpeedPROP_xilxPreTrceAdvAnaPROP_xilxPreTrceRptLimitPROP_xilxPreTrceRptPROP_CurrentFloorplanFilePROP_xilxBitgCfg_GenOpt_MaskFilePROP_xilxBitgCfg_GenOpt_ReadBackPROP_xilxBitgCfg_GenOpt_LogicAllocFilePROP_xilxBitgReadBk_GenBitStrPROP_xilxBitgReadBk_SecEnable Readback and ReconfigurationPROP_xilxBitgStart_Clk_DriveDonePROP_xilxBitgStart_Clk_RelDLLDefault (NoWait)PROP_xilxBitgStart_Clk_WrtEnPROP_xilxBitgStart_Clk_EnOutDefault (5)PROP_xilxBitgStart_Clk_DoneDefault (4)PROP_xilxBitgStart_IntDonePROP_xilxBitgStart_ClkCCLKPROP_xilxBitgCfg_Code0xFFFFFFFFPROP_xilxBitgCfg_UnusedPull DownPROP_xilxBitgCfg_TMSPull UpPROP_xilxBitgCfg_TDOPROP_xilxBitgCfg_TDIPROP_xilxBitgCfg_TCKPROP_xilxBitgCfg_DonePROP_xilxBitgCfg_PgmPROP_xilxBitgCfg_M2PROP_xilxBitgCfg_M1PROP_xilxBitgCfg_M0PROP_xilxBitgCfg_ClkPROP_bitgen_otherCmdLineOptionsPROP_xilxBitgCfg_GenOpt_DbgBitStrPROP_xilxBitgCfg_GenOpt_CompressPROP_xilxBitgCfg_GenOpt_ASCIIFilePROP_xilxBitgCfg_GenOpt_BinaryFilePROP_xilxBitgCfg_GenOpt_BitFilePROP_xilxBitgCfg_GenOpt_DRCPROP_parMpprNodelistFilePROP_xilxPARstratNormal Place and RouteAll files (*)|*PROP_parMpprResultsDirectoryPROP_parMpprResultsToSavePROP_parMpprParIterationsPROP_mpprRsltToCopyPROP_par_otherCmdLineOptionsPROP_parPowerActivityFilePROP_parPowerReductionPROP_parGenSimModelPROP_parGenTimingRptPROP_parGenClkRegionRptPROP_parGenAsyDlyRptPROP_xilxPARuseBondedIOPROP_parTimingModePerformance EvaluationPROP_parIgnoreTimingConstraintsNon Timing DrivenPROP_parUseTimingConstraintsPROP_xilxPARplacerCostTablePROP_xilxPARextraEffortLevelPROP_xilxPARrouterEffortLevelPROP_xilxPARplacerEffortLevelPROP_xilxPAReffortLevelPROP_map_otherCmdLineOptionsPROP_xilxMapSliceLogicInUnusedBRAMsPROP_xilxMapPackfactorPROP_xilxMapDisableRegOrderingPROP_xilxMapPackRegIntoFor Inputs and OutputsPROP_mapUseRLOCConstraintsPROP_xilxMapReportDetailPROP_xilxMapCoverModeAreaPROP_xilxMapAllowLogicOptPROP_xilxMapReplicateLogicPROP_xilxMapTrimUnconnSigPROP_xilxNgdbldPresHierarchyPROP_xilxNgdbldURPROP_xilxNgdbldUnexpBlksPROP_xilxNgdbldIOPadsPROP_xilxNgdbldNTTypeTimestampPROP_ngdbuildUseLOCConstraintsPROP_mapTimingModePROP_mapIgnoreTimingConstraintsPROP_lockPinsUcfFilePROP_Enable_Incremental_MessagingPROP_Enable_Message_FilteringPROP_Enable_Message_CapturePROP_FitterReportFormatHTMLPROP_FlowDebugLevelPROP_UserConstraintEditorPreferenceConstraints EditorPROP_UserEditorCustomSettingPROP_UserEditorPreferenceISE Text EditorPROP_XplorerModeOffPROP_SimModelAutoInsertGlblModuleInNetlistPROP_SimModelGenMultiHierFilePROP_SimModelRetainHierarchyPROP_netgenPostSynthesisSimModelNamePROP_PostSynthSimModelName_synthesis.vPROP_SimModelIncUnisimInVerilogFilePROP_SimModelIncSimprimInVerilogFilePROP_xstSafeImplementPROP_SynthFsmEncodePROP_XPowerOtherXPowerOptsPROP_XPowerOptInputTclScriptPROP_XPowerOptLoadPCFFileDefaultPROP_XPowerOptLoadVCDFilePROP_XPowerOptOutputFilePROP_XPowerOptLoadXMLFilePROP_XPowerOptMaxNumberLinesPROP_XPowerOptVerboseRptPROP_XPowerOptAdvancedVerboseRptPROP_xstNetlistHierarchyAs OptimizedPROP_xilxSynthKeepHierarchyPROP_xilxNgdbldMacroPROP_xilxNgdbld_AULPROP_SynthXORCollapsePROP_ngdbuild_otherCmdLineOptionsPROP_impactPortAuto - defaultUSB 2USB 1LPT 3LPT 2LPT 1PROP_impactConfigModeDesktop ConfigurationSelect MAPSlave SerialBoundary ScanPROP_impactBaud5760038400192009600PROP_ibiswriterShowAllModelsPROP_ISimOtherCompilerOptions_parPROP_ISimOtherCompilerOptions_behavPROP_ISimCustomCompilationOrderFilePROP_ISimUseCustomCompilationOrderPROP_ISimLibSearchOrderFilePROP_ISimSpecifyDefMacroAndValueChkSyntaxPROP_isimSpecifyDefMacroAndValuePROP_ISimSpecifySearchDirectoryChkSyntaxPROP_isimSpecifySearchDirectoryPROP_isimValueRangeCheckPROP_ISimSDFTimingToBeReadSetup TimePROP_ISimVCDFileName_par_tbwxpower.vcdPROP_ISimGenVCDFile_par_tbwPROP_ISimUseCustomSimCmdFile_par_tbwPROP_ISimVCDFileName_par_tbPROP_ISimGenVCDFile_par_tbPROP_ISimUseCustomSimCmdFile_par_tbPROP_ISimStoreAllSignalTransitions_behav_tbwPROP_ISimUseCustomSimCmdFile_behav_tbwPROP_ISimStoreAllSignalTransitions_behav_tbPROP_ISimUseCustomSimCmdFile_behav_tbPROP_ISimStoreAllSignalTransitions_par_tbwPROP_ISimStoreAllSignalTransitions_par_tbPROP_ISimSimulationRunTime_behav_tbwPROP_ISimSimulationRun_behav_tbwPROP_ISimSimulationRunTime_behav_tbPROP_ISimSimulationRun_behav_tbPROP_ISimSimulationRunTime_par_tbwPROP_ISimSimulationRun_par_tbwPROP_ISimSimulationRunTime_par_tbPROP_ISimSimulationRun_par_tbPROP_isimCompileForHdlDebugPROP_isimIncreCompilationPROP_ISimCustomSimCmdFileName_gen_tbwPROP_ISimUseCustomSimCmdFile_gen_tbwPROP_ISimCustomSimCmdFileName_behav_tbwPROP_ISimCustomSimCmdFileName_behav_tbPROP_ISimCustomSimCmdFileName_par_tbwPROP_ISimCustomSimCmdFileName_par_tbPROP_ISimUutInstNameUUTPROP_xstEquivRegRemovalPROP_xilxSynthAddIObufPROP_SynthResSharingPROP_SynthCaseImplStylePROP_xstBusDelimiter<>PROP_xstHierarchySeparator/PROP_xstGenerateRTLNetlistPROP_xst_otherCmdLineOptionsPROP_xstVerilogMacrosPROP_xstGenericsParametersPROP_xstUserCompileListPROP_xstVerilog2001PROP_xstIniFilePROP_xstWorkDir./xstPROP_xstCaseMaintainPROP_xstLibSearchOrderPROP_xstUseSynthConstFilePROP_SynthConstraintsFileCST files (*.cst)|*.cstXCF files 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artitions.html" label="Partition Report" >   <view program="map" inputState="Translated" type="IOBProperties" file="serirq_host_map.mrp" label="IOB Properties" />   <view program="par" inputState="Mapped" type="ConstraintsData" file="serirq_host.par" label="Timing Constraints" />   <view program="par" inputState="Mapped" type="PinoutData" file="serirq_host.pad" label="Pinout Report" />   <view program="par" inputState="Mapped" type="ClocksData" file="serirq_host.par" label="Clock Report" />  </viewgroup>  <viewgroup label="Errors and Warnings" >   <view program="xst" type="MessageList" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" hideColumns="Filtered" />   <view program="ngdbuild" inputState="Synthesized" type="MessageList" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" hideColumns="Filtered" />   <view program="map" inputState="Translated" type="MessageList" file="_xmsgs/map.xmsgs" label="Map Messages" hideColumns="Filtered" />   <view program="par" inputState="Mapped" type="MessageList" file="_xmsgs/par.xmsgs" label="Place and Route Messages" hideColumns="Filtered" />   <view program="trce" inputState="Routed" type="MessageList" file="_xmsgs/trce.xmsgs" label="Timing Messages" hideColumns="Filtered" />   <view program="bitgen" inputState="Routed" type="MessageList" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" hideColumns="Filtered" />   <view fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/bitgen.xmsgs" program="implementation" inputState="Current" type="MessageList" file="_xmsgs/*.xmsgs" label="All Current Messages" hideColumns="Filtered" />  <viewgroup label="Detailed Reports" >   <view program="xst" type="Report" file="serirq_host.syr" label="Synthesis Report   " >    <toc-item title="Synthesis Options Summary" target="   Synthesis Options Summary   " />    <toc-item title="HDL Compilation" target="   HDL Compilation   " />    <toc-item title="Design Hierarchy Analysis" target="   Design Hierarchy Analysis   " />    <toc-item title="HDL Analysis" target="   HDL Analysis   " />    <toc-item title="HDL Synthesis" target="   HDL Synthesis   " />    <toc-item title="Advanced HDL Synthesis" target="   Advanced HDL Synthesis   " />    <toc-item title="Low Level Synthesis" target="   Low Level Synthesis   " />    <toc-item title="Partition Report" target="   Partition Report     " />    <toc-item title="Final Report" target="   Final Report   " />   <view program="ngdbuild" inputState="Synthesized" type="Report" file="serirq_host.bld" label="Translation Report" >    <toc-item title="Top of Report" target="Release" />    <toc-item title="Command Line" target="Command Line:" />    <toc-item title="Partition Status" target="Partition Implementation Status" />    <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />   <view program="map" inputState="Translated" type="Report" file="serirq_host_map.mrp" label="Map Report" >    <toc-item title="Section 1: Errors" target="Section 1 - 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st_partitions.html" label="Partition Report" >   <view program="map" type="IOBProperties" inputState="Translated" file="wb_dreq_host_map.mrp" label="IOB Properties" />   <view program="par" type="ConstraintsData" inputState="Mapped" file="wb_dreq_host.par" label="Timing Constraints" />   <view program="par" type="PinoutData" inputState="Mapped" file="wb_dreq_host.pad" label="Pinout Report" />   <view program="par" type="ClocksData" inputState="Mapped" file="wb_dreq_host.par" label="Clock Report" />  </viewgroup>  <viewgroup label="Errors and Warnings" >   <view program="xst" type="MessageList" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" hideColumns="Filtered" />   <view program="ngdbuild" type="MessageList" inputState="Synthesized" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" hideColumns="Filtered" />   <view program="map" type="MessageList" inputState="Translated" file="_xmsgs/map.xmsgs" label="Map Messages" hideColumns="Filtered" />   <view program="par" type="MessageList" inputState="Mapped" file="_xmsgs/par.xmsgs" label="Place and Route Messages" hideColumns="Filtered" />   <view program="trce" type="MessageList" inputState="Routed" file="_xmsgs/trce.xmsgs" label="Timing Messages" hideColumns="Filtered" />   <view program="bitgen" type="MessageList" inputState="Routed" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" hideColumns="Filtered" />   <view fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/bitgen.xmsgs" program="implementation" type="MessageList" inputState="Current" file="_xmsgs/*.xmsgs" label="All Current Messages" hideColumns="Filtered" />  <viewgroup label="Detailed Reports" >   <view program="xst" type="Report" file="wb_dreq_host.syr" label="Synthesis Report   " >    <toc-item title="Synthesis Options Summary" target="   Synthesis Options Summary   " />    <toc-item title="HDL Compilation" target="   HDL Compilation   " />    <toc-item title="Design Hierarchy Analysis" target="   Design Hierarchy Analysis   " />    <toc-item title="HDL Analysis" target="   HDL Analysis   " />    <toc-item title="HDL Synthesis" target="   HDL Synthesis   " />    <toc-item title="Advanced HDL Synthesis" target="   Advanced HDL Synthesis   " />    <toc-item title="Low Level Synthesis" target="   Low Level Synthesis   " />    <toc-item title="Partition Report" target="   Partition Report     " />    <toc-item title="Final Report" target="   Final Report   " />   <view program="ngdbuild" type="Report" inputState="Synthesized" file="wb_dreq_host.bld" label="Translation Report" >    <toc-item title="Top of Report" target="Release" />    <toc-item title="Command Line" target="Command Line:" />    <toc-item title="Partition Status" target="Partition Implementation Status" />    <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />   <view program="map" type="Report" inputState="Translated" file="wb_dreq_host_map.mrp" label="Map Report" >    <toc-item title="Section 1: Errors" target="Section 1 - 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