URL https://opencores.org/ocsvn/wb_lpc/wb_lpc/trunk
Subversion Repositories wb_lpc

[/] [wb_lpc/] [trunk/] [sim/] [wb_lpc_sim/] [wb_lpc_sim.ise] - Rev 6

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__OBJSTORE__/PK
__OBJSTORE__/common/PK
'__OBJSTORE__/common/HierarchicalDesign/PK
14/wb_lpc_hostTS_EXPANDEDTS_FRAGCOVEREDTS_PACKEDTS_ROUTEDTS_SYNTHESISwb_lpc_hostPK
 __OBJSTORE__/HierarchicalDesign/PK
__OBJSTORE__/ISimPlugin/PK
(__OBJSTORE__/ISimPlugin/SignalOrdering1/PK

 !"#$%&PK
master_bench/clk_i/wb_lpc_master_bench/wbs_adr_i/wb_lpc_master_bench/wbs_dat_i/wb_lpc_master_bench/wbs_cyc_i/wb_lpc_master_bench/wbs_sel_i/wb_lpc_master_bench/dma_chan_i/wb_lpc_master_bench/wbs_tga_i/wb_lpc_master_bench/nrst_i/wb_lpc_master_bench/dma_tc_iPK
__OBJSTORE__/PnAutoRun/PK
__OBJSTORE__/PnAutoRun/Scripts/PK
namespace eval Dpm {
proc GetIseVersion {} {
   set fsetName "fileset.txt"
   set fsetPath ""
   # Find the file in the Xilinx environment.
   # First, construct the environment path.
   set sep ":"; # Default to UNIX style seperator.
   if {[string compare -length 7 $::tcl_platform(platform) "windows"] == 0} {
      set sep ";"; # Platform is a Windows variant, so use semi-colon.
   }
   set xilinxPath $::env(XILINX)
   if [info exists ::env(MYXILINX)] then {
      set xilinxPath [join [list $::env(MYXILINX) $xilinxPath] $sep]
   }
   # Now look in each path of the path until we find a match.
   foreach xilElem [split $xilinxPath $sep] {
      set checkPath ${xilElem}/$fsetName
      set checkPath [ string map { \\ / } $checkPath ]
      if { [file exists $checkPath] } {
         set fsetPath $checkPath
         break
      }
   }
   if { [string equal $fsetPath ""] } {
      puts "ERROR: Can not determine the ISE software version."
      return ""
   }
   if { [catch { open $fsetPath r } fset] } {
      puts "ERROR: Could not open $fsetPath: $fset"
      return ""
   }
   # have the file open, scan for the version entry.
   set sVersion ""
   while { ![eof $fset] } {
      set line [gets $fset]
      regexp {version=(.*)} $line match sVersion
         # The above doesn't stop looking in the file. This assumes that if
         # there are multiple version entries, the last one is the one we want.
   }
   close $fset
   return $sVersion
}
proc CheckForIron {project_name} {
   
   # Determine if the currently running version of ProjNav is earlier than Jade.
   set version [GetIseVersion]
   set dotLocation [string first "." $version]
   set versionBase [string range $version 0 [expr {$dotLocation - 1}]]
   if {$versionBase < 9} {
      
      # The project file is newer than Iron, so take action to prevent the
      # file from being corrupted.
      # Make the file read-only.
      if {[string compare -length 7 $::tcl_platform(platform) "windows"]} {
         # The above will return 0 for a match to "windows" or "windows64".
         # This is the non-zero part of the if, for lin and sol.
         # Change the permissions to turn off writability.
         file attributes $project_name -permissions a-w
      } else {
         # On Windows, set file to read-only.
         file attributes $project_name -readonly 1
      }      
      
      # And tell the user about it.
      set messageText "WARNING: This project was last saved with a newer version of Project Navigator.\nThe project file will be made read-only so that it will not be invalidated by this version."
      # In the console window
      puts $messageText
      # And with a GUI message box if possible.
      ::xilinx::Dpm::TOE::loadGuiLibraries
      set iInterface 0
      set messageDisplay 0
      if {[catch {
         set iInterface [Xilinx::CitP::GetInstance $::xilinx::GuiI::IMessageDlgID]
         set messageDisplay [$iInterface GetInterface $::xilinx::GuiI::IMessageDlgID]
         if {$messageDisplay != 0} {
            # Managed to get a component to display a dialog, so use it
            set messageTitle "Incompatible Project Version (Newer)"
            set messageType 2
               # 2 corresponds to a warning dialog. TclWrapGuiI_Init.cpp doesn't put the enum into Tcl.
            set messageTimeout 300000
               # in milliseconds, 5 minutes
            set messageReturn [$messageDisplay MessageDlg $messageTitle $messageText $messageType 1 1 $messageTimeout "OK" "" ""]
         }
      } catchResult]} {
         # There was an error, probably because we aren't in a GUI enviroment.
      } else {
         # All is well.
      }
      set messageDisplay 0
      set iInterface 0
   }
      
   return 1
}
}
}
::xilinx::Dpm::CheckForIronPK
__OBJSTORE__/ProjectNavigator/PK
/__OBJSTORE__/ProjectNavigator/dpm_project_main/PK

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Simulator (VHDL/Verilog)Other MixedOther VerilogOther VHDLVCS-MXi MixedVCS-MXi VerilogVCS-MXi VHDLVCS-MX MixedVCS-MX VerilogVCS-MX VHDLNC-Sim MixedNC-Sim VerilogNC-Sim VHDLModelsim-XE VerilogModelsim-XE VHDLModelsim-PE MixedModelsim-PE VerilogModelsim-PE VHDLModelsim-SE MixedModelsim-SE VerilogModelsim-SE VHDLPROP_Synthesis_ToolXST (VHDL/Verilog)PROP_Top_Level_Module_TypeHDLVHDLPROP_DevSpeed-5-4PROP_DevPackagefg320fg456PROP_DevDevicexc3s50xc3s400xc3s1500lxc3s1500xc3s1000lxc3s1000xc3s200tq144pq208ft256PROP_ParSmartGuideFileNamePROP_SmartGuidePROP_TopDesignUnitNCD files (*.ncd)|*.ncdPROP_MapSmartGuideFileNamePROP_ISimSpecifyDefMacroAndValuePROP_ISimSpecifySearchDirectoryPROP_ISimSpecifySearchDirPROP_ISimValueRangeCheckPROP_ISimCompileForHdlDebugPROP_ISimIncreCompilationModule|wb_lpc_master_benchModule|wb_lpc_hostPROP_xstVeriIncludeDirPROP_tbwPostParTestbenchNamePROP_tbwTestbenchTargetLangwb_lpc_master_bench.timesim_tfwPROP_tbwPostMapTestbenchNamewb_lpc_master_bench.map_tfwPROP_tbwPostXlateTestbenchNamewb_lpc_master_bench.translate_tfwPROP_PostParSimModelName_timesim.vPROP_SimModelTargetPROP_PostMapSimModelName_map.vPROP_PostXlateSimModelName_translate.vPROP_SimModelRenTopLevEntToPROP_SimModelGenArchOnlyPROPEXT_xilxBitgCfg_DCIUpdateMode_spartan3As RequiredPROPEXT_xilxBitgCfg_Rate_spartan3Default (6)PROPEXT_xilxSynthAddBufg_spartan3PROPEXT_xilxSynthMaxFanout_virtex2PROPEXT_SynthMultStyle_virtex2AutoPROPEXT_xilxMapGenInputK_virtex24PROP_MapRegDuplicationPROP_xilxMapTimingDrivenPackingPROP_MapLogicOptimizationPROP_MapPlacerCostTablePROP_MapExtraEffortNonePROP_MapEffortLevelMediumHighStandardContinue on ImpossibleNormalPROP_xilxBitgStart_Clk_MatchCyclePROP_xilxBitgCfg_DCMShutdownPROP_xilxBitgCfg_GenOpt_EnableCRCPROP_xilxBitgCfg_GenOpt_IEEE1532FilePROP_xilxBitgCfg_GenOpt_CompressPROP_xilxBitgCfg_GenOpt_ASCIIFilePROP_xilxBitgCfg_GenOpt_BinaryFilePROP_xilxBitgCfg_GenOpt_BitFilePROP_xilxBitgCfg_GenOpt_DRCPROP_parMpprNodelistFilePROP_xilxPARstratNormal Place and RouteAll files (*)|*PROP_parMpprResultsDirectoryPROP_parMpprResultsToSavePROP_parMpprParIterationsPROP_mpprRsltToCopyPROP_par_otherCmdLineOptionsPROP_parPowerReductionPROP_parGenSimModelPROP_parGenTimingRptPROP_parGenClkRegionRptPROP_parGenAsyDlyRptPROP_xilxPARuseBondedIOPROP_parUseTimingConstraintsPROP_xilxPARplacerCostTablePROP_xilxPARextraEffortLevelPROP_xilxPARrouterEffortLevelPROP_xilxPARplacerEffortLevelPROP_xilxPAReffortLevelPROP_map_otherCmdLineOptionsPROP_xilxMapSliceLogicInUnusedBRAMsPROP_xilxMapPackfactorPROP_xilxMapDisableRegOrderingPROP_xilxMapPackRegIntoFor Inputs and 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(*.cmd)|*.cmdHEX files (*.hex)|*.hexMCS files (*.mcs)|*.mcsEXO files (*.exo)|*.exoCDF files (*.cdf)|*.cdfBIT files (*.bit)|*.bitPROP_AceActiveNamePROP_AutoGenFilePROP_primeTopLevelModulePROP_primeCorrelateOutputPROP_primeFlatternOutputNetlistPROP_primetimeBlockRamDataPROP_xilxPostTrceTSIFilePROP_xilxPostTrceStampPROP_PostTrceFastPathPROP_xilxPostTrceUncovPathPROP_xilxPostTrceSpeedAbsolute MinPROP_xilxPostTrceAdvAnaPROP_xilxPostTrceRptLimitPROP_xilxPostTrceRptError ReportPROP_PreTrceFastPathPROP_xilxPreTrceUncovPathPROP_xilxPreTrceSpeedPROP_xilxPreTrceAdvAnaPROP_xilxPreTrceRptLimitPROP_xilxPreTrceRptPROP_CurrentFloorplanFilePROP_xilxBitgCfg_GenOpt_MaskFilePROP_xilxBitgCfg_GenOpt_ReadBackPROP_xilxBitgCfg_GenOpt_LogicAllocFilePROP_xilxBitgReadBk_GenBitStrPROP_xilxBitgReadBk_SecEnable Readback and ReconfigurationPROP_xilxBitgStart_Clk_DriveDonePROP_xilxBitgStart_Clk_RelDLLDefault (NoWait)PROP_xilxBitgStart_Clk_WrtEnPROP_xilxBitgStart_Clk_EnOutDefault (5)PROP_xilxBitgStart_Clk_DoneDefault (4)PROP_xilxBitgStart_IntDonePROP_xilxBitgStart_ClkCCLKPROP_xilxBitgCfg_Code0xFFFFFFFFPROP_xilxBitgCfg_UnusedPull DownPROP_xilxBitgCfg_TMSPull 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