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<h1>WisboneTK</h1>
<h2>WishboneTK two-way arbiter</h2>
<h3>Description</h3>
<strong>WishboneTK two-way arbiter</strong> connectrs two master devices to a set of shared slave devies. From the master devices point
of view the shared peripherials will look like a single slave inserted into their local slave's chain. From the shared slaves point of
view the arbiter will act as a master device on behalf of the two real masters. The core is 100% Wishbone compatible
with the <a href="wb_extensions.shtml">WishboneTK extensions</a>. Address select and data buses should be multiplexed to the
common interface externaly but handshake signals are handled by the core. Multiplexer control signals are also provided. The core
is asyncronous to support zero-wait-state operation on the shared bus. Thus the CLK_I signal, required for most Wishbone devies
is not used.
 
<h3>Wishbone datasheet</h3>
<table border>
<tr><th>Description</th><th>Specification</th></tr>
<tr><td>General Description             </td><td>Two-way arbiter.</td></tr>
<tr><td>Supported cycles                </td><td>Slave read/write<br>Slave block read/write<br>Slave rmw<br>
												 Master read/write<br>Master block read/write<br>Master rmw<br></td></tr>
<tr><td>Data port size                  </td><td>n/a</td></tr>
<tr><td>Data port granularity           </td><td>n/a</td></tr>
<tr><td>Data port maximum operand size  </td><td>n/a</td></tr>
<tr><td>Data transfer ordering          </td><td>n/a</td></tr>
<tr><td>Data transfer sequencing        </td><td>n/a</td></tr>
<tr><td>Supported signal list and cross reference to equivalent Wishbone signals</td><td>
	<table width="100%">
	<tr><th>Signal name</th><th>Wishbone equiv.</th></tr>
	<tr><td>RST_I       </td><td>RST_I</td></tr>
	<tr><th colspan="2">Signals to connect to master A</th></tr>
	<tr><td>A_CYC_I       </td><td>CYC_I</td></tr>
	<tr><td>A_STB_I       </td><td>STB_I</td></tr>
	<tr><td>A_WE_I        </td><td>WE_I </td></tr>
	<tr><td>A_ACK_O       </td><td>ACK_O</td></tr>
	<tr><td>A_RTY_O       </td><td>RTY_O</td></tr>
	<tr><td>A_ERR_O       </td><td>ERR_O</td></tr>
	<tr><th colspan="2">Signals to connect to master B</th></tr>
	<tr><td>B_CYC_I       </td><td>CYC_I</td></tr>
	<tr><td>B_STB_I       </td><td>STB_I</td></tr>
	<tr><td>B_WE_I        </td><td>WE_I </td></tr>
	<tr><td>B_ACK_O       </td><td>ACK_O</td></tr>
	<tr><td>B_RTY_O       </td><td>RTY_O</td></tr>
	<tr><td>B_ERR_O       </td><td>ERR_O</td></tr>
	<tr><th colspan="2">Signals to connect to shared slaves</th></tr>
	<tr><td>S_CYC_O       </td><td>CYC_O</td></tr>
	<tr><td>S_STB_O       </td><td>STB_O</td></tr>
	<tr><td>S_WE_O        </td><td>WE_O </td></tr>
	<tr><td>S_ACK_I       </td><td>ACK_I</td></tr>
	<tr><td>S_RTY_I       </td><td>RTY_I</td></tr>
	<tr><td>S_ERR_I       </td><td>ERR_I</td></tr>
	</table>
</table>
<h3>Signal description</h3>
<table border>
<tr><th>Signal name</th><th>Description</th></tr>
<!-- SLAVE SIGNALS -->
<tr><th colspan="2">Signals to connect to master A</th></tr>
<tr><td>A_RST_I       </td><td>Wishbone reset signal</td></tr>
<tr><td>A_CYC_I       </td><td>Wishbone cycle signal. High value frames blocks of access</td></tr>
<tr><td>A_STB_I       </td><td>Wishbone strobe signal. High value indicates cycle to this particular device</td></tr>
<tr><td>A_WE_I        </td><td>Wishbone write enable signal. High indicates data flowing from master to slave</td></tr>
<tr><td>A_ACK_O       </td><td>Wishbone acknowledge signal. High indicates that slave finished operation sucessfully</td></tr>
<tr><td>A_ACK_OI      </td><td>WhisboneTK acknowledge chain input signal</td></tr>
<tr><td>A_RTY_O       </td><td>Wishbone retry signal. High indicates that slave requests retry of the <strong>last cycle in the block</strong>.</td></tr>
<tr><td>A_RTY_OI      </td><td>WhisboneTK retry chain input signal</td></tr>
<tr><td>A_ERR_O       </td><td>Wishbone error signal. High indicates that slave cannot complete the <strong>last cycle in the block</strong>.</td></tr>
<tr><td>A_ERR_OI      </td><td>WhisboneTK error chain input signal</td></tr>
<tr><th colspan="2">Signals to connect to master B</th></tr>
<tr><td>B_RST_I       </td><td>Wishbone reset signal</td></tr>
<tr><td>B_CYC_I       </td><td>Wishbone cycle signal. High value frames blocks of access</td></tr>
<tr><td>B_STB_I       </td><td>Wishbone strobe signal. High value indicates cycle to this particular device</td></tr>
<tr><td>B_WE_I        </td><td>Wishbone write enable signal. High indicates data flowing from master to slave</td></tr>
<tr><td>B_ACK_O       </td><td>Wishbone acknowledge signal. High indicates that slave finished operation sucessfully</td></tr>
<tr><td>B_ACK_OI      </td><td>WhisboneTK acknowledge chain input signal</td></tr>
<tr><td>B_RTY_O       </td><td>Wishbone retry signal. High indicates that slave requests retry of the <strong>last cycle in the block</strong>.</td></tr>
<tr><td>B_RTY_OI      </td><td>WhisboneTK retry chain input signal</td></tr>
<tr><td>B_ERR_O       </td><td>Wishbone error signal. High indicates that slave cannot complete the <strong>last cycle in the block</strong>.</td></tr>
<tr><td>B_ERR_OI      </td><td>WhisboneTK error chain input signal</td></tr>
<tr><th colspan="2">Signals to connect to shared slaves</th></tr>
<tr><td>S_CYC_O       </td><td>Wishbone cycle signal. High value frames blocks of access</td></tr>
<tr><td>S_STB_O       </td><td>Wishbone strobe signal. High value indicates cycle to this particular device</td></tr>
<tr><td>S_WE_O        </td><td>Wishbone write enable signal. High indicates data flowing from master to slave</td></tr>
<tr><td>S_ACK_I       </td><td>Wishbone acknowledge signal. High indicates that slave finished operation sucessfully</td></tr>
<tr><td>S_RTY_I       </td><td>Wishbone retry signal. High indicates that slave requests retry of the <strong>last cycle in the block</strong>.</td></tr>
<tr><td>S_ERR_I       </td><td>Wishbone error signal. High indicates that slave cannot complete the <strong>last cycle in the block</strong>.</td></tr>
</td></tr></table>
 
<h2>Author & Maintainer</h2>
<p>
<a href="/people/tantos">Andras Tantos</a>
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