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<h1>WisboneTK</h1>
<h2>WishboneTK output register</h2>
<h3>Description</h3>
<strong>WishboneTK output register</strong> is a parametrized output register with read-back support. It is 100% Wishbone compatible
with the <a href="wb_extensions.shtml">WishboneTK extensions</a>. The bus-width and the output width can be configured separately. 
Output width can be larger than the bus size. In that case address signals should be used access various parts of the 
however the bus width is required to be bigger than the output width.
 
<h3>Wishbone datasheet</h3>
<table border>
<tr><th>Description</th><th>Specification</th></tr>
<tr><td>General Description             </td><td>Output register with readback support.</td></tr>
<tr><td>Supported cycles                </td><td>Slave read/write<br>Slave block read/write<br>Slave rmw</td></tr>
<tr><td>Data port size                  </td><td>variable</td></tr>
<tr><td>Data port granularity           </td><td>8 bits</td></tr>
<tr><td>Data port maximum operand size  </td><td>same as bus size</td></tr>
<tr><td>Data transfer ordering          </td><td>n/a</td></tr>
<tr><td>Data transfer sequencing        </td><td>n/a</td></tr>
<tr><td>Supported signal list and cross reference to equivalent Wishbone signals</td><td>
	<table width="100%">
	<tr><th>Signal name</th><th>Wishbone equiv.</th></tr>
	<tr><td>CLK_I       </td><td>CLK_I</td></tr>
	<tr><td>RST_I       </td><td>RST_I</td></tr>
	<tr><td>CYC_I       </td><td>CYC_I</td></tr>
	<tr><td>STB_I       </td><td>STB_I</td></tr>
	<tr><td>WE_I        </td><td>WE_I </td></tr>
	<tr><td>ACK_O       </td><td>ACK_O</td></tr>
	<tr><td>SEL_I(..)   </td><td>SEL_I()</td></tr>
	<tr><td>ADR_I(..)   </td><td>ADR_I()</td></tr>
	<tr><td>DAT_I()     </td><td>DAT_I()</td></tr>
	<tr><td>DAT_O()     </td><td>DAT_O()</td></tr>
	</table>
</table>
<h3>Parameter description</h3>
<table border>
<tr><th>Parameter name</th><th>Description</th></tr>
<tr><td>width</td><td>Number of bits in the output register</td></tr>
<tr><td>bus_width</td><td>Size of the data-bus</td></tr>
<tr><td>offset</td><td>Bit-offset from where the output bits start within the data</td></tr>
</table>
<h3>Signal description</h3>
<table border>
<tr><th>Signal name               </th><th>Description</th></tr>
<tr><td>CLK_I                     </td><td>Wishbone clock signal</td></tr>
<tr><td>RST_I                     </td><td>Wishbone reset signal</td></tr>
<tr><td>CYC_I                     </td><td>Wishbone cycle signal. High value frames blocks of access</td></tr>
<tr><td>STB_I                     </td><td>Wishbone strobe signal. High value indicates cycle to this particular device</td></tr>
<tr><td>WE_I                      </td><td>Wishbone write enable signal. High indicates data flowing from master to slave</td></tr>
<tr><td>ACK_O                     </td><td>Wishbone acknowledge signal. High indicates that slave finished operation sucessfully</td></tr>
<tr><td>ACK_OI                    </td><td>WhisboneTK acknowledge chain input signal</td></tr>
<tr><td>SEL_I(bus_width/8-1..0)   </td><td>Wishbone byte-selection signals</td></tr>
<tr><td>ADR_I(addr_width<sup>*</sup>-1..0)    </td><td>Wishbone address bus signals</td></tr>
<tr><td>DAT_I(bus_width-1..0)     </td><td>Wishbone data bus input (to slave direction) signals</td></tr>
<tr><td>DAT_O(bus_width-1..0)     </td><td>Wishbone data bus output (to master direction) signals</td></tr>
<tr><td>DAT_OI(bus_width-1..0)    </td><td>WhisboneTK data bus chain input signal</td></tr>
<tr><td>RST_VAL(width-1..0)       </td><td>Value written to the register upon reset</td></tr>
<tr><td>Q(width-1..0)             </td><td>Output value of the register</td></tr>
</td></tr></table>
<p>
<strong>* addr_with:</strong> size2bits((width+offset+bus_width-1)/bus_width)-1.
 
<h2>Author & Maintainer</h2>
<p>
<a href="/people/tantos">Andras Tantos</a>
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