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<h1>Wishbone Monitor Controller</h1>
<strong>Wishbone Monitor Controller</strong> is a set of freely available VHDL cores. It contains
a central building block containing the basic functionality. It can then be sorrounded by
various helper functions to add functionality. The central core comprises of a
sync generator, a pixel data generator, a memory interface and a CPU interface. It is specificly
designed for slow 8-bit systems (although CPU interface size can be set) with no high needs 
about a display. It is also designed to be simple and small (cheap). The target is the whole 
design to be well fit in an Altera ACEX 1k30 device which is available for around 10USD.
<h2>Individual module decriptions</h2>
Building blocks
    <li><a href="vga_core.shtml">Central core</a></li>
    <li><a href="palette.shtml">Palette RAM module</a></li>
    <li><a href="accel.shtml">Accelerator</a></li>
    <li><a href="mouse.shtml">Mouse sprite module</a></li>
Sampe configurations
    <li><a href="vga_chip.shtml">VGA chip</a></li>
    <li><a href="vga_core_v2.shtml">Accelerated VGA core</a></li>
For a fast breafing here are the main design goals and features of the various modules:
	<li>Highly customizable sync generation with polarity control</li>
	<li>Capable of driving EGA/VGA/Hercules/CGA monitors</li>
	<li>Multi-scan support for low resolution modes</li>
	<li>Internal memory for multi-scan, for even less memory accesses</li>
	<li>FIFO de-coupled memory interface and pixel output circuit</li>
	<li>Wisbone pixel memory interface</li>
	<li>16-bit pixel memory support (later parametrizable)</li>
	<li>Programmable color depth (1,2,4,8 bits per pixel)</li>
	<li>~80Mhz pixel clock (wish)</li>
	<li>Standard parametrizable Wishbone CPU bus interface</li>
	<li>Syncron internal structure</li>
	<li>Fully synthesizable (using Leonardo Spectrum)</li>
	<li>Palette support (3x5 bits plus key bit in each entry)</li>
	<li>Accelerator functions for common display operations</li>
	<li>Mouse cursor support if it fits to the chip (wish)</li>
	<li>Central core implemented</li>
	<li>Palette and Accelerator implemented</li>
	<li>Cores compile under ActiveHDL and Leonardo Spectrum</li>
	<li>Cores simulate well (some more validation still needed)</li>
	<li>All functionality fits into a 1k30 chip</li>
	<li>Synthesized central core works as expected but max. clock rate is ~60MHz</li>
	<li>When all function synthesized max. clock rate is ~35MHz :-(((</li>
	<li>More simulation to proove all core functionality</li>
	<li>Port to other (Xilinx Spartan-II) FPGA architectures</li>
	<li>Optimize design to encrease clock speed</li>
	<li>Implement Mouse sprite block</li>
	<li>More sample applications (complete designs)</li>
	<li>Sample programs</li>
	<li>Parametrizable pixel memory interface</li>
	<li>Generic version for fixed configuration (even much smaller)</li>
	<li>LCD support (??)</li>
	<li>high-color support (??)</li>
	<li>Develop a target board and try the core in real</li>
The first beta version of the Memory Controller can be downloaded from from the CVS repository.
You can browse the repository <a href="/cvsweb.shtml/wb_vga/">here</a> or
use <a href="/cvsmodule.shtml">CVSget</a> with module name <strong>wb_vga</strong>.
The design uses the <a href="/cores/wb_tk/">WishboneTK</a> so you will also need that.
<h2>Author & Maintainer</h2>
<a href="/people/tantos">Andras Tantos</a>
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