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<h1>Wishbone Monitor Controller Palette RAM</h1>
<strong>Wishbone Monitor Controller Palette RAM</strong> is a small piece of
dual-ported memory. One of the interfaces is a Wishbone compatible interface
with the <a href="/cores/wb_tk/wb_extensions.shtml">WishboneTK extensions</a>.
This interface is write-only. Any read operations attempted on the port would
result in an error (ERR_O goes active). The other port is an asyncronous
read-only port. For that port an enable signal is (BLANK) provided. If that signal
is active all output bits are driven to 0. Otherwise the output will be the data
stored in the memory location identified by the address provided. This type of
memory is ideal for palette memory in a monitor controller.
<h3>Wishbone datasheet</h3>
<table border>
<tr><td>General Description             </td><td>Monitor controller palette RAM.</td></tr>
<tr><td>Supported cycles                </td><td>Slave read/write<br>Slave block read/write<br>Slave rmw<br></td></tr>
<tr><td>Data port size                  </td><td>Configurable</td></tr>
<tr><td>Data port granularity           </td><td>Bus size</td></tr>
<tr><td>Data port maximum operand size  </td><td>Bus size</td></tr>
<tr><td>Data transfer ordering          </td><td>n/a</td></tr>
<tr><td>Data transfer sequencing        </td><td>n/a</td></tr>
<tr><td>Supported signal list and cross reference to equivalent Wishbone signals</td><td>
	<tr><th>Signal name</th><th>Wishbone equiv.</th></tr>
	<tr><td>CLK_I       </td><td>CLK_I</td></tr>
	<tr><td>RST_I       </td><td>RST_I</td></tr>
	<tr><td>CYC_I       </td><td>CYC_I</td></tr>
	<tr><td>STB_I       </td><td>STB_I</td></tr>
	<tr><td>WE_I        </td><td>WE_I </td></tr>
	<tr><td>ACK_O       </td><td>ACK_O</td></tr>
	<tr><td>ERR_O       </td><td>ERR_O</td></tr>
	<tr><td>ADR_I(..)   </td><td>ADR_I()</td></tr>
	<tr><td>DAT_I(..)   </td><td>DAT_I()</td></tr>
	<tr><td>DAT_O(..)   </td><td>DAT_O()</td></tr>
<h3>Parameter description</h3>
<table border>
<tr><td>Parameter name</th><th>Description</th></tr>
<tr><td>v_dat_width   </td><td>True-color pixel output width</td></tr>
<tr><td>v_adr_width   </td><td>Palettized pixel input width</td></tr>
<tr><td>cpu_dat_width </td><td>CPU data width</td></tr>
<tr><td>cpu_adr_width </td><td>CPU address width</td></tr>
<h3>Signal description</h3>
<table border>
<tr><th>Signal name</th><th>Description</th></tr>
<tr><th colspan="2">Signals to connect to the pixel memory master</th></tr>
<tr><td>CYC_I       </td><td>Wishbone cycle signal. High value frames blocks of access</td></tr>
<tr><td>STB_I       </td><td>Wishbone strobe signal. High value indicates cycle to this particular device</td></tr>
<tr><td>WE_I        </td><td>Wishbone write enable signal. High indicates data flowing from master to slave</td></tr>
<tr><td>ACK_O       </td><td>Wishbone acknowledge signal. High indicates that slave finished operation sucessfully</td></tr>
<tr><td>ACK_OI      </td><td>WhisboneTK acknowledge chain input signal</td></tr>
<tr><td>ERR_O       </td><td>Wishbone error signal. High indicates that slave cannot complete the <strong>last cycle in the block</strong>.</td></tr>
<tr><td>ERR_OI      </td><td>WhisboneTK error chain input signal</td></tr>
<tr><td>ADR_I(cpu_adr_width-1..0)  </td><td>Wishbone address bus signals</td></tr>
<tr><td>DAT_I(cpu_dat_width-1..0)   </td><td>Wishbone data bus input (to slave direction) signals</td></tr>
<tr><td>DAT_O(cpu_dat_width-1..0)   </td><td>Wishbone data bus output (to master direction) signals</td></tr>
<tr><td>DAT_OI(cpu_dat_width-1..0)  </td><td>WhisboneTK data bus chain input signal</td></tr>
<tr><th colspan="2">Non Wishbone signals</th></tr>
<tr><td>BLANK </td><td>Blanking input signal. If active (high) output is forced to all 0s</td></tr>
<tr><td>V_DAT_I(v_adr_width-1 DOWNTO 0)</td><td>Palettized data input</td></tr>
<tr><td>V_DAT_O(v_dat_width-1 DOWNTO 0)</td><td>True-color data output</td></tr>
<h2>Author & Maintainer</h2>
<a href="/people/tantos">Andras Tantos</a>
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