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////////////////////////////////////////////////////////////////////////////////
//
// Filename: 	wbddrsdram.v
//
// Project:	A wishbone controlled DDR3 SDRAM memory controller.
// Used in:	OpenArty, an entirely open SoC based upon the Arty platform
//
// Purpose:	To control a DDR3-1333 (9-9-9) memory from a wishbone bus.
//		In our particular implementation, there will be two command
//	clocks (2.5 ns) per FPGA clock (i_clk) at 5 ns, and 64-bits transferred
//	per FPGA clock.  However, since the memory is focused around 128-bit
//	word transfers, attempts to transfer other than adjacent 64-bit words
//	will (of necessity) suffer stalls.  Please see the documentation for
//	more details of how this controller works.
//
// Creator:	Dan Gisselquist, Ph.D.
//		Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program.  (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.)  If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License:	GPL, v3, as defined and found on www.gnu.org,
//		http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
 
// Possible commands to the DDR3 memory.  These consist of settings for the
// bits: o_wb_cs_n, o_wb_ras_n, o_wb_cas_n, and o_wb_we_n, respectively.
`define	DDR_MRSET	4'b0000
`define	DDR_REFRESH	4'b0001
`define	DDR_PRECHARGE	4'b0010
`define	DDR_ACTIVATE	4'b0011
`define	DDR_WRITE	4'b0100
`define	DDR_READ	4'b0101
`define	DDR_ZQS		4'b0110
`define	DDR_NOOP	4'b0111
//`define	DDR_DESELECT	4'b1???
//
// In this controller, 24-bit commands tend to be passed around.  These 
// 'commands' are bit fields.  Here we specify the bits associated with
// the bit fields.
`define	DDR_RSTDONE	24	// End the reset sequence?
`define	DDR_RSTTIMER	23	// Does this reset command take multiple clocks?
`define	DDR_RSTBIT	22	// Value to place on reset_n
`define	DDR_CKEBIT	21	// Should this reset command set CKE?
//
// Refresh command bit fields
`define	DDR_PREREFRESH_STALL	24
`define	DDR_NEEDREFRESH	23
`define	DDR_RFTIMER	22
`define	DDR_RFBEGIN	21
//
`define	DDR_CMDLEN	21
`define	DDR_CSBIT	20
`define	DDR_RASBIT	19
`define	DDR_CASBIT	18
`define	DDR_WEBIT	17
`define	DDR_NOPTIMER	16	// Steal this from BA bits
`define	DDR_BABITS	3	// BABITS are really from 18:16, they are 3 bits
`define	DDR_ADDR_BITS	14
//
//
module	wbddrsdram(i_clk, i_reset,
		// Wishbone inputs
		i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
			i_wb_sel,
		// Wishbone outputs
		o_wb_ack, o_wb_stall, o_wb_data,
		// Memory command wires
		o_ddr_reset_n, o_ddr_cke, o_ddr_bus_oe,
		o_ddr_cmd_a, o_ddr_cmd_b, o_ddr_cmd_c, o_ddr_cmd_d,
		// And the data wires to go with them ....
		o_ddr_data, i_ddr_data, o_bus);
	// These parameters are not really meant for adjusting from the
	// top level.  These are more internal variables, recorded here
	// so that things can be automatically adjusted without much
	// problem.
	parameter	CKRP = 0;
	parameter	BUSNOW = 2, BUSREG = BUSNOW-1;
	// The commands (above) include (in this order):
	//	o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n,
	//	o_ddr_dqs, o_ddr_dm, o_ddr_odt
	input		i_clk,	// *MUST* be at 200 MHz for this to work
			i_reset;
	// Wishbone inputs
	input			i_wb_cyc, i_wb_stb, i_wb_we;
	// The bus address needs to identify a single 128-bit word of interest
	input	[23:0]		i_wb_addr;
	input	[127:0]		i_wb_data;
	input	[15:0]		i_wb_sel;
	// Wishbone responses/outputs
	output	reg		o_wb_ack, o_wb_stall;
	output	reg	[127:0]	o_wb_data;
	// DDR memory command wires
	output	reg		o_ddr_reset_n, o_ddr_cke;
	output	reg	[1:0]	o_ddr_bus_oe;
	// CMDs are:
	//	 4 bits of CS, RAS, CAS, WE
	//	 3 bits of bank
	//	14 bits of Address
	//	 1 bit  of DQS (strobe active, or not)
	//	 4 bits of mask (one per byte)
	//	 1 bit  of ODT
	//	----
	//	27 bits total
	output	wire	[26:0]	o_ddr_cmd_a, o_ddr_cmd_b, 
				o_ddr_cmd_c, o_ddr_cmd_d;
	output	reg	[127:0]	o_ddr_data;
	input		[127:0]	i_ddr_data;
	output	reg		o_bus;
	reg		[2:0]	cmd_pipe;
	reg		[1:0]	nxt_pipe;
 
	always @(posedge i_clk)
		o_bus <= (i_wb_cyc)&&(i_wb_stb)&&(!o_wb_stall);
 
 
//////////
//
//
//	Reset Logic
//
//
//////////
//
//
// Reset logic should be simple, and is given as follows:
// note that it depends upon a ROM memory, reset_mem, and an address into that
// memory: reset_address.  Each memory location provides either a "command" to
// the DDR3 SDRAM, or a timer to wait until the next command.  Further, the
// timer commands indicate whether or not the command during the timer is to
// be set to idle, or whether the command is instead left as it was.
	reg		reset_override, reset_ztimer, maintenance_override;
	reg	[3:0]	reset_address;
	reg	[(`DDR_CMDLEN-1):0]	reset_cmd, cmd_a, cmd_b, cmd_c, cmd_d,
					refresh_cmd, maintenance_cmd;
	reg	[24:0]	reset_instruction;
	reg	[16:0]	reset_timer;
	initial	reset_override = 1'b1;
	initial	reset_address  = 4'h0;
	always @(posedge i_clk)
		if (i_reset)
		begin
			reset_override <= 1'b1;
			reset_cmd <= { `DDR_NOOP, reset_instruction[16:0]};
		end else if ((reset_ztimer)&&(reset_override))
		begin
			if (reset_instruction[`DDR_RSTDONE])
				reset_override <= 1'b0;
			reset_cmd <= reset_instruction[20:0];
		end
 
	initial	reset_ztimer = 1'b0;	// Is the timer zero?
	initial	reset_timer = 17'h02;
	always @(posedge i_clk)
		if (i_reset)
		begin
			reset_ztimer <= 1'b0;
			reset_timer <= 17'd2;
		end else if (!reset_ztimer)
		begin
			reset_ztimer <= (reset_timer == 17'h01);
			reset_timer <= reset_timer - 17'h01;
		end else if (reset_instruction[`DDR_RSTTIMER])
		begin
			reset_ztimer <= 1'b0;
			reset_timer <= reset_instruction[16:0];
		end
 
	wire	[16:0]	w_ckXPR, w_ckRFC_first;
	wire	[13:0]	w_MR0, w_MR1, w_MR2;
	assign w_MR0 = 14'h0210;
	assign w_MR1 = 14'h0044;
	assign w_MR2 = 14'h0040;
	assign w_ckXPR = 17'd12;  // Table 68, p186: 56 nCK / 4 sys clks= 14(-2)
	assign	w_ckRFC_first = 17'd11; // i.e. 52 nCK, or ckREFI
	always @(posedge i_clk)
		// DONE, TIMER, RESET, CKE, 
		if (i_reset)
			reset_instruction <= { 4'h4, `DDR_NOOP, 17'd40_000 };
		else if (reset_ztimer) case(reset_address) // RSTDONE, TIMER, CKE, ??
		// 1. Reset asserted (active low) for 200 us. (@80MHz)
		4'h0: reset_instruction <= { 4'h4, `DDR_NOOP, 17'd16_000 };
		// 2. Reset de-asserted, wait 500 us before asserting CKE
		4'h1: reset_instruction <= { 4'h6, `DDR_NOOP, 17'd40_000 };
		// 3. Assert CKE, wait minimum of Reset CKE Exit time
		4'h2: reset_instruction <= { 4'h7, `DDR_NOOP, w_ckXPR };
		// 4. Set MR2.  (4 nCK, no TIMER, but needs a NOOP cycle)
		4'h3: reset_instruction <= { 4'h3, `DDR_MRSET, 3'h2, w_MR2 };
		// 5. Set MR1.  (4 nCK, no TIMER, but needs a NOOP cycle)
		4'h4: reset_instruction <= { 4'h3, `DDR_MRSET, 3'h1, w_MR1 };
		// 6. Set MR0
		4'h5: reset_instruction <= { 4'h3, `DDR_MRSET, 3'h0, w_MR0 };
		// 7. Wait 12 nCK clocks, or 3 sys clocks
		4'h6: reset_instruction <= { 4'h7, `DDR_NOOP,  17'd1 };
		// 8. Issue a ZQCL command to start ZQ calibration, A10 is high
		4'h7: reset_instruction <= { 4'h3, `DDR_ZQS, 6'h0, 1'b1, 10'h0};
		//11.Wait for both tDLLK and tZQinit completed, both are
		// 512 cks. Of course, since every one of these commands takes
		// two clocks, we wait for one quarter as many clocks (minus
		// two for our timer logic)
		4'h8: reset_instruction <= { 4'h7, `DDR_NOOP, 17'd126 };
		// 12. Precharge all command
		4'h9: reset_instruction <= { 4'h3, `DDR_PRECHARGE, 6'h0, 1'b1, 10'h0 };
		// 13. Wait 5 memory clocks (8 memory clocks) for the precharge
		// to complete.  A single NOOP here will have us waiting
		// 8 clocks, so we should be good here.
		4'ha: reset_instruction <= { 4'h3, `DDR_NOOP, 17'd0 };
		// 14. A single Auto Refresh commands
		4'hb: reset_instruction <= { 4'h3, `DDR_REFRESH, 17'h00 };
		// 15. Wait for the auto refresh to complete
		4'hc: reset_instruction <= { 4'h7, `DDR_NOOP, w_ckRFC_first };
		4'hd: reset_instruction <= { 4'h7, `DDR_NOOP, 17'd3 };
		default:
			reset_instruction <={4'hb, `DDR_NOOP, 17'd00_000 };
		endcase
 
	initial	reset_address = 4'h0;
	always @(posedge i_clk)
		if (i_reset)
			reset_address <= 4'h0;
		else if ((reset_ztimer)&&(reset_override)&&(!reset_instruction[`DDR_RSTDONE]))
			reset_address <= reset_address + 4'h1;
 
//////////
//
//
//	Refresh Logic
//
//
//////////
//
//
//
// Okay, let's investigate when we need to do a refresh.  Our plan will be to
// do a single refreshes every tREFI seconds.  We will not push off refreshes,
// nor pull them in--for simplicity.  tREFI = 7.8us, but it is a parameter
// in the number of clocks (2496 nCK).  In our case, 7.8us / 12.5ns = 624 clocks
// (not nCK!)
//
// Note that 160ns are needed between refresh commands (JEDEC, p172), or
// 52 clocks @320MHz.  After this time, no more refreshes will be needed for
// (2496-52) clocks (@ 320 MHz), or (624-13) clocks (@80MHz).
//
// This logic is very similar to the refresh logic, both use a memory as a 
// script.
//
	reg		need_refresh, pre_refresh_stall;
	reg		refresh_ztimer;
	reg	[16:0]	refresh_counter;
	reg	[2:0]	refresh_addr;
	reg	[24:0]	refresh_instruction;
	always @(posedge i_clk)
		if (reset_override)
			refresh_addr <= 3'h0;
		else if (refresh_ztimer)
			refresh_addr <= refresh_addr + 3'h1;
		else if (refresh_instruction[`DDR_RFBEGIN])
			refresh_addr <= 3'h0;
 
	always @(posedge i_clk)
		if (reset_override)
		begin
			refresh_ztimer <= 1'b0;
			refresh_counter <= 17'd4;
		end else if (!refresh_ztimer)
		begin
			refresh_ztimer <= (refresh_counter == 17'h1);
			refresh_counter <= (refresh_counter - 17'h1);
		end else if (refresh_instruction[`DDR_RFTIMER])
		begin
			refresh_ztimer <= 1'b0;
			refresh_counter <= refresh_instruction[16:0];
		end
 
	wire	[16:0]	w_ckREFI;
	assign	w_ckREFI = 17'd1560; // == 6240/4
 
	wire	[16:0]	w_ckREFI_left, w_ckRFC_nxt, w_wait_for_idle,
			w_pre_stall_counts;
 
	// We need to wait for the bus to become idle from whatever state
	// it is in.  The difficult time for this measurement is assuming
	// a write was just given.  In that case, we need to wait for the
	// write to complete, and then to wait an additional tWR (write
	// recovery time) or 6 nCK clocks from the end of the write.  This
	// works out to seven idle bus cycles from the time of the write
	// command, or a count of 5 (7-2).
	assign	w_pre_stall_counts = 17'd3;	//
	assign	w_wait_for_idle = 17'd0;	//
	assign	w_ckREFI_left[16:0] = 17'd624	// The full interval
				-17'd13	 // Minus what we've already waited
				-w_wait_for_idle
				-17'd19;
	assign	w_ckRFC_nxt[16:0] = 17'd12-17'd3;
 
	always @(posedge i_clk)
	if (reset_override)
		refresh_instruction <= { 4'h2, `DDR_NOOP, 17'd1 };
	else if (refresh_ztimer)
		case(refresh_addr)//NEED-REFRESH, HAVE-TIMER, BEGIN(start-over)
		// First, a number of clocks needing no refresh
		3'h0: refresh_instruction <= { 4'h2, `DDR_NOOP, w_ckREFI_left };
		// Then, we take command of the bus and wait for it to be
		// guaranteed idle
		3'h1: refresh_instruction <= { 4'ha, `DDR_NOOP, w_pre_stall_counts };
		3'h2: refresh_instruction <= { 4'hc, `DDR_NOOP, w_wait_for_idle };
		// Once the bus is idle, all commands complete, and a minimum
		// recovery time given, we can issue a precharge all command
		3'h3: refresh_instruction <= { 4'hc, `DDR_PRECHARGE, 17'h0400 };
		// Now we need to wait tRP = 3 clocks (6 nCK)
		3'h4: refresh_instruction <= { 4'hc, `DDR_NOOP, 17'h00 };
		3'h5: refresh_instruction <= { 4'hc, `DDR_REFRESH, 17'h00 };
		3'h6: refresh_instruction <= { 4'he, `DDR_NOOP, w_ckRFC_nxt };
		3'h7: refresh_instruction <= { 4'h2, `DDR_NOOP, 17'd12 };
		// default:
			// refresh_instruction <= { 4'h1, `DDR_NOOP, 17'h00 };
		endcase
 
	// Note that we don't need to check if (reset_override) here since
	// refresh_ztimer will always be true if (reset_override)--in other
	// words, it will be true for many, many, clocks--enough for this
	// logic to settle out.
	always @(posedge i_clk)
		if (refresh_ztimer)
			refresh_cmd <= refresh_instruction[20:0];
	always @(posedge i_clk)
		if (refresh_ztimer)
			need_refresh <= refresh_instruction[`DDR_NEEDREFRESH];
	always @(posedge i_clk)
		if (refresh_ztimer)
			pre_refresh_stall <= refresh_instruction[`DDR_PREREFRESH_STALL];
 
 
 
	reg	[1:0]	drive_dqs;
	// Our chosen timing doesn't require any more resolution than one
	// bus clock for ODT.  (Of course, this really isn't necessary, since
	// we aren't using ODT as per the MRx registers ... but we keep it
	// around in case we change our minds later.)
	reg	[15:0]	ddr_dm;
 
	// The pending transaction
	reg	[127:0]	r_data;
	reg		r_pending, r_we;
	reg	[13:0]	r_row;
	reg	[2:0]	r_bank;
	reg	[9:0]	r_col;
	reg	[15:0]	r_sel;
 
	// The pending transaction, one further into the pipeline.  This is
	// the stage where the read/write command is actually given to the
	// interface if we haven't stalled.
	reg	[127:0]	s_data;
	reg		s_pending, s_we;
	reg	[13:0]	s_row, s_nxt_row;
	reg	[2:0]	s_bank, s_nxt_bank;
	reg	[9:0]	s_col;
	reg	[15:0]	s_sel;
 
	// Can we preload the next bank?
	reg	[13:0]	r_nxt_row;
	reg	[2:0]	r_nxt_bank;
 
 
//////////
//
//
//	Open Banks
//
//
//////////
//
//
//
// Let's keep track of any open banks.  There are 8 of them to keep track of.
//
//	A precharge requires 1 clocks at 80MHz to complete.
//	An activate also requires 1 clocks at 80MHz to complete.
//	By the time we log these, they will be complete.
//	Precharges are not allowed until the maximum of:
//		2 clocks (200 MHz) after a read command
//		4 clocks after a write command
//
//
	wire	w_precharge_all;
	reg	[CKRP:0]	bank_status	[0:7];
	reg	[13:0]	bank_address	[0:7];
 
	always @(posedge i_clk)
	begin
		if (cmd_pipe[0])
		begin
			bank_status[s_bank] <= 1'b0;
			if (nxt_pipe[1])
				bank_status[s_nxt_bank] <= 1'b1;
		end else begin
			if (cmd_pipe[1])
				bank_status[s_bank] <= 1'b1;
			else if (nxt_pipe[1])
				bank_status[s_nxt_bank] <= 1'b1;
			if (nxt_pipe[0])
				bank_status[s_nxt_bank] <= 1'b0;
		end
 
		if (maintenance_override)
		begin
			bank_status[0] <= 1'b0;
			bank_status[1] <= 1'b0;
			bank_status[2] <= 1'b0;
			bank_status[3] <= 1'b0;
			bank_status[4] <= 1'b0;
			bank_status[5] <= 1'b0;
			bank_status[6] <= 1'b0;
			bank_status[7] <= 1'b0;
		end
 
	end
 
	always @(posedge i_clk)
		if (cmd_pipe[1])
			bank_address[s_bank] <= s_row;
		else if (nxt_pipe[1])
			bank_address[s_nxt_bank] <= s_nxt_row;
 
 
//////////
//
//
//	Data BUS information
//
//
//////////
//
//
//	Our purpose here is to keep track of when the data bus will be
//	active.  This is separate from the FIFO which will contain the
//	data to be placed on the bus (when so placed), in that this is
//	a group of shift registers--every position has a location in time,
//	and time always moves forward.  The FIFO, on the other hand, only
//	moves forward when data moves onto the bus.
//
//
 
	reg	[BUSNOW:0]	bus_active, bus_read, bus_ack;
	initial	bus_active = 0;
	initial	bus_ack = 0;
	always @(posedge i_clk)
	begin
		bus_active[BUSNOW:0] <= { bus_active[(BUSNOW-1):0], 1'b0 };
		// Drive the d-bus?
		bus_read[BUSNOW:0]   <= { bus_read[(BUSNOW-1):0], 1'b0 };
		// Will this position on the bus get a wishbone acknowledgement?
		bus_ack[BUSNOW:0]   <= { bus_ack[(BUSNOW-1):0], 1'b0 };
 
		if (cmd_pipe[2])
		begin
			bus_active[0]<= 1'b1; // Data transfers in one clocks
			bus_ack[0] <= 1'b1;
			bus_ack[0] <= 1'b1;
 
			bus_read[0] <= !s_we;
		end
	end
 
//
//
// Now, let's see, can we issue a read command?
//
//
	wire	pre_valid;
	assign	pre_valid = !maintenance_override;
 
	reg	pipe_stall;
 
	always @(posedge i_clk)
	begin
		r_pending <= (i_wb_stb)&&(~o_wb_stall)
				||(r_pending)&&(pipe_stall);
		if (~pipe_stall)
			s_pending <= r_pending;
		if (~pipe_stall)
		begin
			if (r_pending)
			begin
				pipe_stall <= 1'b1;
				o_wb_stall <= 1'b1;
				if (!bank_status[r_bank][0])
					cmd_pipe <= 3'b010;
				else if (bank_address[r_bank] != r_row)
					cmd_pipe <= 3'b001; // Read in two clocks
				else begin
					cmd_pipe <= 3'b100; // Read now
					pipe_stall <= 1'b0;
					o_wb_stall <= 1'b0;
				end
 
				if (!bank_status[r_nxt_bank][0])
					nxt_pipe <= 2'b10;
				else if (bank_address[r_nxt_bank] != r_row)
					nxt_pipe <= 2'b01; // Read in two clocks
				else
					nxt_pipe <= 2'b00; // Next is ready
				if (nxt_pipe[1])
					nxt_pipe[1] <= 1'b0;
			end else begin
				cmd_pipe <= 3'b000;
				nxt_pipe <= { nxt_pipe[0], 1'b0 };
				pipe_stall <= 1'b0;
				o_wb_stall <= 1'b0;
			end
		end else begin // if (pipe_stall)
			pipe_stall <= (s_pending)&&(cmd_pipe[0]);
			o_wb_stall <= (s_pending)&&(cmd_pipe[0]);
			cmd_pipe <= { cmd_pipe[1:0], 1'b0 };
 
			nxt_pipe[0] <= (cmd_pipe[0])&&(nxt_pipe[0]);
			nxt_pipe[1] <= ((cmd_pipe[0])&&(nxt_pipe[0])) ? 1'b0
					: ((cmd_pipe[1])?(|nxt_pipe[1:0]) : nxt_pipe[0]);
		end
		if (pre_refresh_stall)
			o_wb_stall <= 1'b1;
 
		if (~pipe_stall)
		begin
			r_we   <= i_wb_we;
			r_data <= i_wb_data;
			r_row  <= i_wb_addr[23:10]; // 14 bits row address
			r_bank <= i_wb_addr[9:7];
			r_col  <= { i_wb_addr[6:0], 3'b000 }; // 10 bits Caddr
			r_sel  <= i_wb_sel;
 
// i_wb_addr[0] is the  8-bit      byte selector of  16-bits (ignored)
// i_wb_addr[1] is the 16-bit half-word selector of  32-bits (ignored)
// i_wb_addr[2] is the 32-bit      word selector of  64-bits (ignored)
// i_wb_addr[3] is the 64-bit long word selector of 128-bits
 
			// pre-emptive work
			r_nxt_row  <= (i_wb_addr[9:7]==3'h7)
					? (i_wb_addr[23:10]+14'h1)
					: i_wb_addr[23:10];
			r_nxt_bank <= i_wb_addr[9:7]+3'h1;
		end
 
		if (~pipe_stall)
		begin
			// Moving one down the pipeline
			s_we   <= r_we;
			s_data <= r_data;
			s_row  <= r_row;
			s_bank <= r_bank;
			s_col  <= r_col;
			s_sel  <= (r_we)?(~r_sel):16'h00;
 
			// pre-emptive work
			s_nxt_row  <= r_nxt_row;
			s_nxt_bank <= r_nxt_bank;
		end
	end
 
 
//
//
// Okay, let's look at the last assignment in our chain.  It should look
// something like:
	always @(posedge i_clk)
		if (i_reset)
			o_ddr_reset_n <= 1'b0;
		else if (reset_ztimer)
			o_ddr_reset_n <= reset_instruction[`DDR_RSTBIT];
	always @(posedge i_clk)
		if (i_reset)
			o_ddr_cke <= 1'b0;
		else if (reset_ztimer)
			o_ddr_cke <= reset_instruction[`DDR_CKEBIT];
 
	always @(posedge i_clk)
		if (i_reset)
			maintenance_override <= 1'b1;
		else
			maintenance_override <= (reset_override)||(need_refresh);
 
	initial	maintenance_cmd = { `DDR_NOOP, 17'h00 };
	always @(posedge i_clk)
		if (i_reset)
			maintenance_cmd <= { `DDR_NOOP, 17'h00 };
		else
			maintenance_cmd <= (reset_override)?reset_cmd:refresh_cmd;
 
 
	always @(posedge i_clk)
	begin
		// We run our commands by timeslots, A, B, C, and D in that
		// order.
 
		// Timeslot A always contains any maintenance commands we might
		//	 have.
		// Timeslot B always contains any precharge command, excluding
		//	the maintenance precharge-all command.
		// Timeslot C always contains any activate command
		// Timeslot D always contains any read/write command
		//
		// We can always set these commands to whatever, to reduce the
		// used logic, as long as the top bit (CS_N) is used to select
		// whether or not the command is active.  If CS_N is 0 the
		// command will be applied by the chip, if 1 the command turns
		// into a deselect command that the chip will ignore.
		//
		cmd_a <= maintenance_cmd;
 
		cmd_b <= { `DDR_PRECHARGE, s_nxt_bank, s_nxt_row[13:11], 1'b0, s_nxt_row[9:0] };
		cmd_b[`DDR_CSBIT] <= 1'b1; // Deactivate, unless ...
		if (cmd_pipe[0])
			cmd_b <= { `DDR_PRECHARGE, s_bank, s_row[13:11], 1'b0, s_row[9:0] };
		cmd_b[`DDR_CSBIT] <= (!cmd_pipe[0])&&(!nxt_pipe[0]);
 
		cmd_c <= { `DDR_ACTIVATE, s_nxt_bank, s_nxt_row[13:11], 1'b0, s_nxt_row[9:0] };
		cmd_c[`DDR_CSBIT] <= 1'b1; // Disable command, unless ...
		if (cmd_pipe[1])
			cmd_c <= { `DDR_ACTIVATE, s_bank, s_row[13:0] };
		else if (nxt_pipe[1])
			cmd_c[`DDR_CSBIT] <= 1'b0;
 
		if (cmd_pipe[2])
		begin
			cmd_d[`DDR_CSBIT:`DDR_WEBIT] <= (s_we)?`DDR_WRITE:`DDR_READ;
			cmd_d[(`DDR_WEBIT-1):0] <= { s_bank, 3'h0, 1'b0, s_col };
		end
		cmd_d[`DDR_CSBIT] <= !(cmd_pipe[2]);
 
 
		// Now, if the maintenance mode must override whatever we are
		// doing, we only need to apply this more complicated logic
		// to the CS_N bit, or bit[20], since this will activate or
		// deactivate the rest of the command--making the rest
		// either relevant (CS_N=0) or irrelevant (CS_N=1) as we need.
		if (maintenance_override)
		begin // Over-ride all commands.  Make them deselect commands,
			// save for the maintenance timeslot.
			cmd_a[`DDR_CSBIT] <= 1'b0;
			cmd_b[`DDR_CSBIT] <= 1'b1;
			cmd_c[`DDR_CSBIT] <= 1'b1;
			cmd_d[`DDR_CSBIT] <= 1'b1;
		end else
			cmd_a[`DDR_CSBIT] <= 1'b1; // Disable maintenance timeslot
	end
 
`define	LGFIFOLN	3
`define	FIFOLEN		8
	reg	[(`LGFIFOLN-1):0]	bus_fifo_head, bus_fifo_tail;
	reg	[127:0]	bus_fifo_data	[0:(`FIFOLEN-1)];
	reg	[15:0]	bus_fifo_sel	[0:(`FIFOLEN-1)];
	reg		pre_ack;
 
	// The bus R/W FIFO
	wire	w_bus_fifo_read_next_transaction;
	assign	w_bus_fifo_read_next_transaction = (bus_ack[BUSREG]);
	always @(posedge i_clk)
	begin
		pre_ack <= 1'b0;
		if (reset_override)
		begin
			bus_fifo_head <= {(`LGFIFOLN){1'b0}};
			bus_fifo_tail <= {(`LGFIFOLN){1'b0}};
		end else begin
			if ((s_pending)&&(!pipe_stall))
				bus_fifo_head <= bus_fifo_head + 1'b1;
 
			if (w_bus_fifo_read_next_transaction)
			begin
				bus_fifo_tail <= bus_fifo_tail + 1'b1;
				pre_ack <= 1'b1;
			end
		end
		bus_fifo_data[bus_fifo_head] <= s_data;
		bus_fifo_sel[bus_fifo_head] <= s_sel;
	end
 
 
	always @(posedge i_clk)
		o_ddr_data  <= bus_fifo_data[bus_fifo_tail];
	always @(posedge i_clk)
		ddr_dm   <= (bus_ack[BUSREG])? bus_fifo_sel[bus_fifo_tail]
			: ((!bus_read[BUSREG])? 16'hffff: 16'h0000);
	always @(posedge i_clk)
	begin
		drive_dqs[1] <= (bus_active[(BUSREG)])
			&&(!bus_read[(BUSREG)]);
		drive_dqs[0] <= (bus_active[BUSREG:(BUSREG-1)] != 2'b00)
			&&(bus_read[BUSREG:(BUSREG-1)] == 2'b00);
		//
		// Is the strobe on during the last clock?
		o_ddr_bus_oe[0] <= (|bus_active[BUSREG:(BUSREG-1)])&&(!bus_read[BUSREG]);
		// Is data transmitting the bus throughout?
		o_ddr_bus_oe[1] <= (bus_active[BUSREG])&&(!bus_read[BUSREG]);
	end
 
	// First command
	assign	o_ddr_cmd_a = { cmd_a, drive_dqs[1], ddr_dm[15:12], drive_dqs[0] };
	// Second command (of four)
	assign	o_ddr_cmd_b = { cmd_b, drive_dqs[1], ddr_dm[11: 8], drive_dqs[0] };
	// Third command (of four)
	assign	o_ddr_cmd_c = { cmd_c, drive_dqs[1], ddr_dm[ 7: 4], drive_dqs[0] };
	// Fourth command (of four)--occupies the last timeslot
	assign	o_ddr_cmd_d = { cmd_d, drive_dqs[0], ddr_dm[ 3: 0], drive_dqs[0] };
 
	assign	w_precharge_all = (cmd_a[`DDR_CSBIT:`DDR_WEBIT]==`DDR_PRECHARGE)
				&&(cmd_a[10]);
 
	always @(posedge i_clk)
		o_wb_ack <= pre_ack;
	always @(posedge i_clk)
		o_wb_data <= i_ddr_data;
 
endmodule