URL
https://opencores.org/ocsvn/wiegand_ctl/wiegand_ctl/trunk
Subversion Repositories wiegand_ctl
[/] [wiegand_ctl/] [trunk/] [syn/] [altera/] [wiegand_tx/] [db/] [wiegand_tx_top.map.qmsg] - Rev 17
Compare with Previous | Blame | View Log
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1424102367754 ""}{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 14.0.0 Build 200 06/17/2014 SJ Web Edition " "Version 14.0.0 Build 200 06/17/2014 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1424102367754 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Feb 16 10:59:27 2015 " "Processing started: Mon Feb 16 10:59:27 2015" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1424102367754 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1424102367754 ""}{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off wiegand_tx_top -c wiegand_tx_top " "Command: quartus_map --read_settings_files=on --write_settings_files=off wiegand_tx_top -c wiegand_tx_top" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1424102367754 ""}{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1424102368175 ""}{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "bit wiegand_tx_top.v(110) " "Verilog HDL Declaration warning at wiegand_tx_top.v(110): \"bit\" is SystemVerilog-2005 keyword" { } { { "../../../rtl/verilog/wiegand_tx_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/wiegand_tx_top.v" 110 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 0 0 "Quartus II" 0 -1 1424102368269 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/jeffa/desktop/rtl/wiegand/trunk/rtl/verilog/wiegand_tx_top.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/jeffa/desktop/rtl/wiegand/trunk/rtl/verilog/wiegand_tx_top.v" { { "Info" "ISGN_ENTITY_NAME" "1 wiegand_tx_top " "Found entity 1: wiegand_tx_top" { } { { "../../../rtl/verilog/wiegand_tx_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/wiegand_tx_top.v" 56 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1424102368269 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1424102368269 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/jeffa/desktop/rtl/wiegand/trunk/rtl/verilog/wiegand_defines.v 0 0 " "Found 0 design units, including 0 entities, in source file /users/jeffa/desktop/rtl/wiegand/trunk/rtl/verilog/wiegand_defines.v" { } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1424102368269 ""}{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "wb_interface.v(187) " "Verilog HDL warning at wb_interface.v(187): extended using \"x\" or \"z\"" { } { { "../../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/wb_interface.v" 187 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1424102368285 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/jeffa/desktop/rtl/wiegand/trunk/rtl/verilog/wb_interface.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/jeffa/desktop/rtl/wiegand/trunk/rtl/verilog/wb_interface.v" { { "Info" "ISGN_ENTITY_NAME" "1 wb_interface_wieg " "Found entity 1: wb_interface_wieg" { } { { "../../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/wb_interface.v" 57 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1424102368285 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1424102368285 ""}{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "fifos.v(223) " "Verilog HDL warning at fifos.v(223): extended using \"x\" or \"z\"" { } { { "../../../rtl/verilog/fifos.v" "" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/fifos.v" 223 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1424102368285 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/jeffa/desktop/rtl/wiegand/trunk/rtl/verilog/fifos.v 3 3 " "Found 3 design units, including 3 entities, in source file /users/jeffa/desktop/rtl/wiegand/trunk/rtl/verilog/fifos.v" { { "Info" "ISGN_ENTITY_NAME" "1 fifo_wieg " "Found entity 1: fifo_wieg" { } { { "../../../rtl/verilog/fifos.v" "" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/fifos.v" 71 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1424102368300 ""} { "Info" "ISGN_ENTITY_NAME" "2 custom_fifo_dp " "Found entity 2: custom_fifo_dp" { } { { "../../../rtl/verilog/fifos.v" "" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/fifos.v" 130 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1424102368300 ""} { "Info" "ISGN_ENTITY_NAME" "3 mem_byte " "Found entity 3: mem_byte" { } { { "../../../rtl/verilog/fifos.v" "" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/fifos.v" 204 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1424102368300 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1424102368300 ""}{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "wb_wr_en wiegand_tx_top.v(235) " "Verilog HDL Implicit Net warning at wiegand_tx_top.v(235): created implicit net for \"wb_wr_en\"" { } { { "../../../rtl/verilog/wiegand_tx_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/wiegand_tx_top.v" 235 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1424102368300 ""}{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "empty wiegand_tx_top.v(235) " "Verilog HDL Implicit Net warning at wiegand_tx_top.v(235): created implicit net for \"empty\"" { } { { "../../../rtl/verilog/wiegand_tx_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/wiegand_tx_top.v" 235 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1424102368300 ""}{ "Info" "ISGN_START_ELABORATION_TOP" "wiegand_tx_top " "Elaborating entity \"wiegand_tx_top\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1424102368331 ""}{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 wiegand_tx_top.v(141) " "Verilog HDL assignment warning at wiegand_tx_top.v(141): truncated value with size 32 to match size of target (5)" { } { { "../../../rtl/verilog/wiegand_tx_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/wiegand_tx_top.v" 141 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1424102368331 "|wiegand_tx_top"}{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 wiegand_tx_top.v(155) " "Verilog HDL assignment warning at wiegand_tx_top.v(155): truncated value with size 32 to match size of target (7)" { } { { "../../../rtl/verilog/wiegand_tx_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/wiegand_tx_top.v" 155 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1424102368331 "|wiegand_tx_top"}{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 wiegand_tx_top.v(161) " "Verilog HDL assignment warning at wiegand_tx_top.v(161): truncated value with size 32 to match size of target (7)" { } { { "../../../rtl/verilog/wiegand_tx_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/wiegand_tx_top.v" 161 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1424102368331 "|wiegand_tx_top"}{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fifo_wieg fifo_wieg:datafifowrite " "Elaborating entity \"fifo_wieg\" for hierarchy \"fifo_wieg:datafifowrite\"" { } { { "../../../rtl/verilog/wiegand_tx_top.v" "datafifowrite" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/wiegand_tx_top.v" 235 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424102368394 ""}{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "custom_fifo_dp fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp5 " "Elaborating entity \"custom_fifo_dp\" for hierarchy \"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp5\"" { } { { "../../../rtl/verilog/fifos.v" "custom_fifo_dp5" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/fifos.v" 112 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424102368441 ""}{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mem_byte fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp5\|mem_byte:mem\[0\].mem_byte " "Elaborating entity \"mem_byte\" for hierarchy \"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp5\|mem_byte:mem\[0\].mem_byte\"" { } { { "../../../rtl/verilog/fifos.v" "mem\[0\].mem_byte" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/fifos.v" 161 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424102368487 ""}{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "wb_interface_wieg wb_interface_wieg:wb_interface " "Elaborating entity \"wb_interface_wieg\" for hierarchy \"wb_interface_wieg:wb_interface\"" { } { { "../../../rtl/verilog/wiegand_tx_top.v" "wb_interface" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/wiegand_tx_top.v" 242 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1424102368550 ""}{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "6 1 wb_interface.v(144) " "Verilog HDL assignment warning at wb_interface.v(144): truncated value with size 6 to match size of target (1)" { } { { "../../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/wb_interface.v" 144 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1424102368550 "|wiegand_tx_top|wb_interface_wieg:wb_interface"}{ "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR_HDR" "" "Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp8\|mem_byte_out\[7\]\" " "Converted tri-state node \"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp8\|mem_byte_out\[7\]\" into a selector" { } { { "../../../rtl/verilog/fifos.v" "" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/fifos.v" 169 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Quartus II" 0 -1 1424102369299 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp8\|mem_byte_out\[6\]\" " "Converted tri-state node \"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp8\|mem_byte_out\[6\]\" into a selector" { } { { "../../../rtl/verilog/fifos.v" "" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/fifos.v" 169 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector"0 0 "Quartus II" 0 -1 1424102369299 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp8\|mem_byte_out\[5\]\" " "Converted tri-state node \"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp8\|mem_byte_out\[5\]\" into a selector" { } { { "../../../rtl/verilog/fifos.v" "" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/fifos.v" 169 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Quartus II" 0 -1 1424102369299 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp8\|mem_byte_out\[4\]\" " "Converted tri-state node \"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp8\|mem_byte_out\[4\]\" into a selector" { } { { "../../../rtl/verilog/fifos.v" "" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/fifos.v" 169 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Quartus II" 0 -1 1424102369299 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp8\|mem_byte_out\[3\]\" " "Converted tri-state node \"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp8\|mem_byte_out\[3\]\" into a selector" { } { { "../../../rtl/verilog/fifos.v" "" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/fifos.v" 169 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Quartus II" 0 -1 1424102369299 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp8\|mem_byte_out\[2\]\" " "Converted tri-state node \"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp8\|mem_byte_out\[2\]\" into a selector" { } { { "../../../rtl/verilog/fifos.v" "" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/fifos.v" 169 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Quartus II" 0 -1 1424102369299 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp8\|mem_byte_out\[1\]\" " "Converted tri-state node \"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp8\|mem_byte_out\[1\]\" into a selector" { } { { "../../../rtl/verilog/fifos.v" "" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/fifos.v" 169 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Quartus II" 0 -1 1424102369299 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp8\|mem_byte_out\[0\]\" " "Converted tri-state node \"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp8\|mem_byte_out\[0\]\" into a selector" { } { { "../../../rtl/verilog/fifos.v" "" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/fifos.v" 169 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Quartus II" 0 -1 1424102369299 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp7\|mem_byte_out\[7\]\" " "Converted tri-state node \"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp7\|mem_byte_out\[7\]\" into a selector" { } { { "../../../rtl/verilog/fifos.v" "" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/fifos.v" 169 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Quartus II" 0 -1 1424102369299 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp7\|mem_byte_out\[6\]\" " "Converted tri-state node \"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp7\|mem_byte_out\[6\]\" into a selector" { } { { "../../../rtl/verilog/fifos.v" "" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/fifos.v" 169 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Quartus II" 0 -1 1424102369299 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp7\|mem_byte_out\[5\]\" " "Converted tri-state node \"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp7\|mem_byte_out\[5\]\" into a selector" { } { { "../../../rtl/verilog/fifos.v" "" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/fifos.v" 169 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Quartus II" 0 -1 1424102369299 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp7\|mem_byte_out\[4\]\" " "Converted tri-state node \"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp7\|mem_byte_out\[4\]\" into a selector" { } { { "../../../rtl/verilog/fifos.v" "" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/fifos.v" 169 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Quartus II" 0 -1 1424102369299 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp7\|mem_byte_out\[3\]\" " "Converted tri-state node \"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp7\|mem_byte_out\[3\]\" into a selector" { } { { "../../../rtl/verilog/fifos.v" "" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/fifos.v" 169 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Quartus II" 0 -1 1424102369299 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp7\|mem_byte_out\[2\]\" " "Converted tri-state node \"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp7\|mem_byte_out\[2\]\" into a selector" { } { { "../../../rtl/verilog/fifos.v" "" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/fifos.v" 169 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Quartus II" 0 -1 1424102369299 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp7\|mem_byte_out\[1\]\" " "Converted tri-state node \"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp7\|mem_byte_out\[1\]\" into a selector" { } { { "../../../rtl/verilog/fifos.v" "" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/fifos.v" 169 -1 0 }} } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Quartus II" 0 -1 1424102369299 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp7\|mem_byte_out\[0\]\" " "Converted tri-state node \"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp7\|mem_byte_out\[0\]\" into a selector" { } { { "../../../rtl/verilog/fifos.v" "" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/fifos.v" 169 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Quartus II" 0 -1 1424102369299 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp6\|mem_byte_out\[7\]\" " "Converted tri-state node \"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp6\|mem_byte_out\[7\]\" into a selector" { } { { "../../../rtl/verilog/fifos.v" "" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/fifos.v" 169 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Quartus II" 0 -1 1424102369299 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp6\|mem_byte_out\[6\]\" " "Converted tri-state node \"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp6\|mem_byte_out\[6\]\" into a selector" { } { { "../../../rtl/verilog/fifos.v" "" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/fifos.v" 169 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Quartus II" 0 -1 1424102369299 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp6\|mem_byte_out\[5\]\" " "Converted tri-state node \"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp6\|mem_byte_out\[5\]\" into a selector" { } { { "../../../rtl/verilog/fifos.v" "" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/fifos.v" 169 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Quartus II" 0 -1 1424102369299 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp6\|mem_byte_out\[4\]\" " "Converted tri-state node \"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp6\|mem_byte_out\[4\]\" into a selector" { } { { "../../../rtl/verilog/fifos.v" "" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/fifos.v" 169 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Quartus II" 0 -1 1424102369299 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp6\|mem_byte_out\[3\]\" " "Converted tri-state node \"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp6\|mem_byte_out\[3\]\" into a selector" { } { { "../../../rtl/verilog/fifos.v" "" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/fifos.v" 169 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Quartus II" 0 -1 1424102369299 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp6\|mem_byte_out\[2\]\" " "Converted tri-state node \"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp6\|mem_byte_out\[2\]\" into a selector" { } { { "../../../rtl/verilog/fifos.v" "" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/fifos.v" 169 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Quartus II" 0 -1 1424102369299 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp6\|mem_byte_out\[1\]\" " "Converted tri-state node \"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp6\|mem_byte_out\[1\]\" into a selector" { } { { "../../../rtl/verilog/fifos.v" "" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/fifos.v" 169 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Quartus II" 0 -1 1424102369299 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp6\|mem_byte_out\[0\]\" " "Converted tri-state node \"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp6\|mem_byte_out\[0\]\" into a selector" { } { { "../../../rtl/verilog/fifos.v" "" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/fifos.v" 169 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Quartus II" 0 -1 1424102369299 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp5\|mem_byte_out\[7\]\" " "Converted tri-state node \"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp5\|mem_byte_out\[7\]\" into a selector" { } { { "../../../rtl/verilog/fifos.v" "" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/fifos.v" 169 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Quartus II" 0 -1 1424102369299 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp5\|mem_byte_out\[6\]\" " "Converted tri-state node \"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp5\|mem_byte_out\[6\]\" into a selector" { } { { "../../../rtl/verilog/fifos.v" "" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/fifos.v" 169 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Quartus II" 0 -1 1424102369299 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp5\|mem_byte_out\[5\]\" " "Converted tri-state node \"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp5\|mem_byte_out\[5\]\" into a selector" { } { { "../../../rtl/verilog/fifos.v" "" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/fifos.v" 169 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Quartus II" 0 -1 1424102369299 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp5\|mem_byte_out\[4\]\" " "Converted tri-state node \"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp5\|mem_byte_out\[4\]\" into a selector" { } { { "../../../rtl/verilog/fifos.v" "" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/fifos.v" 169 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Quartus II" 0 -1 1424102369299 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp5\|mem_byte_out\[3\]\" " "Converted tri-state node \"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp5\|mem_byte_out\[3\]\" into a selector" { } { { "../../../rtl/verilog/fifos.v" "" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/fifos.v" 169 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Quartus II" 0 -1 1424102369299 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp5\|mem_byte_out\[2\]\" " "Converted tri-state node \"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp5\|mem_byte_out\[2\]\" into a selector" { } { { "../../../rtl/verilog/fifos.v" "" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/fifos.v" 169 -1 0 } } }0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Quartus II" 0 -1 1424102369299 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp5\|mem_byte_out\[1\]\" " "Converted tri-state node \"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp5\|mem_byte_out\[1\]\" into a selector" { } { { "../../../rtl/verilog/fifos.v" "" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/fifos.v" 169 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "Quartus II" 0 -1 1424102369299 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_SELECTOR" "\"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp5\|mem_byte_out\[0\]\" " "Converted tri-state node \"fifo_wieg:datafifowrite\|custom_fifo_dp:custom_fifo_dp5\|mem_byte_out\[0\]\" into a selector" { } { { "../../../rtl/verilog/fifos.v" "" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/fifos.v" 169 -1 0 } } } 0 13048 "Converted tri-state node %1!s! into a selector" 0 0 "QuartusII" 0 -1 1424102369299 ""} } { } 0 13046 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "Quartus II" 0 -1 1424102369299 ""}{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "../../../rtl/verilog/wiegand_tx_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/wiegand_tx_top.v" 76 -1 0 } } { "../../../rtl/verilog/wiegand_tx_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/wiegand_tx_top.v" 77 -1 0 } } { "../../../rtl/verilog/wb_interface.v" "" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/wb_interface.v" 164 -1 0 } } { "../../../rtl/verilog/fifos.v" "" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/fifos.v" 183 -1 0 } } { "../../../rtl/verilog/fifos.v" "" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/fifos.v" 175 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "Quartus II" 0 -1 1424102369985 ""}{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" { } { } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Quartus II" 0 -1 1424102370001 ""}{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1424102370203 ""}{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "3 " "3 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1424102370687 ""}{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/altera/wiegand_tx/output_files/wiegand_tx_top.map.smsg " "Generated suppressed messages file C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/altera/wiegand_tx/output_files/wiegand_tx_top.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1424102370749 ""}{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1424102370968 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1424102370968 ""}{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "7 " "Design contains 7 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "wb_cti_i\[0\] " "No output dependent on input pin \"wb_cti_i\[0\]\"" { } { { "../../../rtl/verilog/wiegand_tx_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/wiegand_tx_top.v" 87 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1424102371108 "|wiegand_tx_top|wb_cti_i[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "wb_cti_i\[1\] " "No output dependent on input pin \"wb_cti_i\[1\]\"" { } { { "../../../rtl/verilog/wiegand_tx_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/wiegand_tx_top.v" 87 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1424102371108 "|wiegand_tx_top|wb_cti_i[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "wb_cti_i\[2\] " "No output dependent on input pin \"wb_cti_i\[2\]\"" { } { { "../../../rtl/verilog/wiegand_tx_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/wiegand_tx_top.v" 87 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1424102371108 "|wiegand_tx_top|wb_cti_i[2]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "wb_sel_i\[0\] " "No output dependent on input pin \"wb_sel_i\[0\]\"" { } { { "../../../rtl/verilog/wiegand_tx_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/wiegand_tx_top.v" 86 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1424102371108 "|wiegand_tx_top|wb_sel_i[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "wb_sel_i\[1\] " "No output dependent on input pin \"wb_sel_i\[1\]\"" { } { { "../../../rtl/verilog/wiegand_tx_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/wiegand_tx_top.v" 86 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1424102371108 "|wiegand_tx_top|wb_sel_i[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "wb_sel_i\[2\] " "No output dependent on input pin \"wb_sel_i\[2\]\"" { } { { "../../../rtl/verilog/wiegand_tx_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/wiegand_tx_top.v" 86 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1424102371108 "|wiegand_tx_top|wb_sel_i[2]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "wb_sel_i\[3\] " "No output dependent on input pin \"wb_sel_i\[3\]\"" { } { { "../../../rtl/verilog/wiegand_tx_top.v" "" { Text "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/wiegand_tx_top.v" 86 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1424102371108 "|wiegand_tx_top|wb_sel_i[3]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1424102371108 ""}{ "Info" "ICUT_CUT_TM_SUMMARY" "498 " "Implemented 498 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "50 " "Implemented 50 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1424102371108 ""} { "Info" "ICUT_CUT_TM_OPINS" "37 " "Implemented 37 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1424102371108 ""} { "Info" "ICUT_CUT_TM_LCELLS" "411 " "Implemented 411 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1424102371108 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1424102371108 ""}{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 49 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 49 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "583 " "Peak virtual memory: 583 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1424102371171 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Feb 16 10:59:31 2015 " "Processing ended: Mon Feb 16 10:59:31 2015" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1424102371171 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1424102371171 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1424102371171 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1424102371171 ""}