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[/] [wiegand_ctl/] [trunk/] [syn/] [altera/] [wiegand_tx/] [output_files/] [wiegand_tx_top.eda.rpt] - Rev 17
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EDA Netlist Writer report for wiegand_tx_topMon Feb 16 11:00:08 2015Quartus II 64-Bit Version 14.0.0 Build 200 06/17/2014 SJ Web Edition---------------------; Table of Contents ;---------------------1. Legal Notice2. EDA Netlist Writer Summary3. Simulation Settings4. Simulation Generated Files5. EDA Netlist Writer Messages----------------; Legal Notice ;----------------Copyright (C) 1991-2014 Altera Corporation. All rights reserved.Your use of Altera Corporation's design tools, logic functionsand other software and tools, and its AMPP partner logicfunctions, and any output files from any of the foregoing(including device programming or simulation files), and anyassociated documentation or information are expressly subjectto the terms and conditions of the Altera Program LicenseSubscription Agreement, the Altera Quartus II License Agreement,the Altera MegaCore Function License Agreement, or otherapplicable license agreement, including, without limitation,that your use is for the sole purpose of programming logicdevices manufactured by Altera and sold by Altera or itsauthorized distributors. Please refer to the applicableagreement for further details.+-------------------------------------------------------------------+; EDA Netlist Writer Summary ;+---------------------------+---------------------------------------+; EDA Netlist Writer Status ; Successful - Mon Feb 16 11:00:08 2015 ;; Revision Name ; wiegand_tx_top ;; Top-level Entity Name ; wiegand_tx_top ;; Family ; Cyclone IV GX ;; Simulation Files Creation ; Successful ;+---------------------------+---------------------------------------++-------------------------------------------------------------------------------------------------------------------------------+; Simulation Settings ;+---------------------------------------------------------------------------------------------------+---------------------------+; Option ; Setting ;+---------------------------------------------------------------------------------------------------+---------------------------+; Tool Name ; ModelSim-Altera (Verilog) ;; Generate netlist for functional simulation only ; Off ;; Time scale ; 1 ps ;; Truncate long hierarchy paths ; Off ;; Map illegal HDL characters ; Off ;; Flatten buses into individual nodes ; Off ;; Maintain hierarchy ; Off ;; Bring out device-wide set/reset signals as ports ; Off ;; Enable glitch filtering ; Off ;; Do not write top level VHDL entity ; Off ;; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ;; Architecture name in VHDL output netlist ; structure ;; Generate third-party EDA tool command script for RTL functional simulation ; Off ;; Generate third-party EDA tool command script for gate-level simulation ; Off ;+---------------------------------------------------------------------------------------------------+---------------------------++----------------------------------------------------------------------------------------------------------------------------+; Simulation Generated Files ;+----------------------------------------------------------------------------------------------------------------------------+; Generated Files ;+----------------------------------------------------------------------------------------------------------------------------+; C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/altera/wiegand_tx/simulation/modelsim/wiegand_tx_top_6_1200mv_85c_slow.vo ;; C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/altera/wiegand_tx/simulation/modelsim/wiegand_tx_top_6_1200mv_0c_slow.vo ;; C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/altera/wiegand_tx/simulation/modelsim/wiegand_tx_top_min_1200mv_0c_fast.vo ;; C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/altera/wiegand_tx/simulation/modelsim/wiegand_tx_top.vo ;; C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/altera/wiegand_tx/simulation/modelsim/wiegand_tx_top_6_1200mv_85c_v_slow.sdo ;; C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/altera/wiegand_tx/simulation/modelsim/wiegand_tx_top_6_1200mv_0c_v_slow.sdo ;; C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/altera/wiegand_tx/simulation/modelsim/wiegand_tx_top_min_1200mv_0c_v_fast.sdo ;; C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/altera/wiegand_tx/simulation/modelsim/wiegand_tx_top_v.sdo ;+----------------------------------------------------------------------------------------------------------------------------++-----------------------------+; EDA Netlist Writer Messages ;+-----------------------------+Info: *******************************************************************Info: Running Quartus II 64-Bit EDA Netlist WriterInfo: Version 14.0.0 Build 200 06/17/2014 SJ Web EditionInfo: Processing started: Mon Feb 16 11:00:06 2015Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off wiegand_tx_top -c wiegand_tx_topInfo (204019): Generated file wiegand_tx_top_6_1200mv_85c_slow.vo in folder "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/altera/wiegand_tx/simulation/modelsim/" for EDA simulation toolInfo (204019): Generated file wiegand_tx_top_6_1200mv_0c_slow.vo in folder "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/altera/wiegand_tx/simulation/modelsim/" for EDA simulation toolInfo (204019): Generated file wiegand_tx_top_min_1200mv_0c_fast.vo in folder "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/altera/wiegand_tx/simulation/modelsim/" for EDA simulation toolInfo (204019): Generated file wiegand_tx_top.vo in folder "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/altera/wiegand_tx/simulation/modelsim/" for EDA simulation toolInfo (204019): Generated file wiegand_tx_top_6_1200mv_85c_v_slow.sdo in folder "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/altera/wiegand_tx/simulation/modelsim/" for EDA simulation toolInfo (204019): Generated file wiegand_tx_top_6_1200mv_0c_v_slow.sdo in folder "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/altera/wiegand_tx/simulation/modelsim/" for EDA simulation toolInfo (204019): Generated file wiegand_tx_top_min_1200mv_0c_v_fast.sdo in folder "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/altera/wiegand_tx/simulation/modelsim/" for EDA simulation toolInfo (204019): Generated file wiegand_tx_top_v.sdo in folder "C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/altera/wiegand_tx/simulation/modelsim/" for EDA simulation toolInfo: Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warningsInfo: Peak virtual memory: 511 megabytesInfo: Processing ended: Mon Feb 16 11:00:08 2015Info: Elapsed time: 00:00:02Info: Total CPU time (on all processors): 00:00:02