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[/] [wiegand_ctl/] [trunk/] [syn/] [altera/] [wiegand_tx/] [output_files/] [wiegand_tx_top.map.rpt] - Rev 17

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Analysis & Synthesis report for wiegand_tx_top
Mon Feb 16 10:59:31 2015
Quartus II 64-Bit Version 14.0.0 Build 200 06/17/2014 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Parallel Compilation
  5. Analysis & Synthesis Source Files Read
  6. Analysis & Synthesis Resource Usage Summary
  7. Analysis & Synthesis Resource Utilization by Entity
  8. State Machine - |wiegand_tx_top|state
  9. Registers Removed During Synthesis
 10. General Register Statistics
 11. Inverted Register Statistics
 12. Multiplexer Restructuring Statistics (Restructuring Performed)
 13. Port Connectivity Checks: "fifo_wieg:datafifowrite"
 14. Post-Synthesis Netlist Statistics for Top Partition
 15. Elapsed Time Per Partition
 16. Analysis & Synthesis Messages
 17. Analysis & Synthesis Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, the Altera Quartus II License Agreement,
the Altera MegaCore Function License Agreement, or other 
applicable license agreement, including, without limitation, 
that your use is for the sole purpose of programming logic 
devices manufactured by Altera and sold by Altera or its 
authorized distributors.  Please refer to the applicable 
agreement for further details.



+---------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                    ;
+------------------------------------+--------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Mon Feb 16 10:59:31 2015      ;
; Quartus II 64-Bit Version          ; 14.0.0 Build 200 06/17/2014 SJ Web Edition ;
; Revision Name                      ; wiegand_tx_top                             ;
; Top-level Entity Name              ; wiegand_tx_top                             ;
; Family                             ; Cyclone IV GX                              ;
; Total logic elements               ; 409                                        ;
;     Total combinational functions  ; 242                                        ;
;     Dedicated logic registers      ; 303                                        ;
; Total registers                    ; 303                                        ;
; Total pins                         ; 87                                         ;
; Total virtual pins                 ; 0                                          ;
; Total memory bits                  ; 0                                          ;
; Embedded Multiplier 9-bit elements ; 0                                          ;
; Total GXB Receiver Channel PCS     ; 0                                          ;
; Total GXB Receiver Channel PMA     ; 0                                          ;
; Total GXB Transmitter Channel PCS  ; 0                                          ;
; Total GXB Transmitter Channel PMA  ; 0                                          ;
; Total PLLs                         ; 0                                          ;
+------------------------------------+--------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                        ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                     ; Setting            ; Default Value      ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Top-level entity name                                                      ; wiegand_tx_top     ; wiegand_tx_top     ;
; Family name                                                                ; Cyclone IV GX      ; Cyclone IV GX      ;
; Use smart compilation                                                      ; Off                ; Off                ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
; Enable compact report table                                                ; Off                ; Off                ;
; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
; Preserve fewer node names                                                  ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
; Verilog Version                                                            ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
; State Machine Processing                                                   ; Auto               ; Auto               ;
; Safe State Machine                                                         ; Off                ; Off                ;
; Extract Verilog State Machines                                             ; On                 ; On                 ;
; Extract VHDL State Machines                                                ; On                 ; On                 ;
; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
; Infer RAMs from Raw Logic                                                  ; On                 ; On                 ;
; Parallel Synthesis                                                         ; On                 ; On                 ;
; DSP Block Balancing                                                        ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                         ; On                 ; On                 ;
; Power-Up Don't Care                                                        ; On                 ; On                 ;
; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
; Remove Duplicate Registers                                                 ; On                 ; On                 ;
; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
; Optimization Technique                                                     ; Balanced           ; Balanced           ;
; Carry Chain Length                                                         ; 70                 ; 70                 ;
; Auto Carry Chains                                                          ; On                 ; On                 ;
; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                      ; Off                ; Off                ;
; Auto ROM Replacement                                                       ; On                 ; On                 ;
; Auto RAM Replacement                                                       ; On                 ; On                 ;
; Auto DSP Block Replacement                                                 ; On                 ; On                 ;
; Auto Shift Register Replacement                                            ; Auto               ; Auto               ;
; Allow Shift Register Merging across Hierarchies                            ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
; Strict RAM Replacement                                                     ; Off                ; Off                ;
; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
; Auto RAM Block Balancing                                                   ; On                 ; On                 ;
; Auto RAM to Logic Cell Conversion                                          ; Off                ; Off                ;
; Auto Resource Sharing                                                      ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                              ; Off                ; Off                ;
; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
; Timing-Driven Synthesis                                                    ; On                 ; On                 ;
; Report Parameter Settings                                                  ; On                 ; On                 ;
; Report Source Assignments                                                  ; On                 ; On                 ;
; Report Connectivity Checks                                                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                               ; Normal compilation ; Normal compilation ;
; HDL message level                                                          ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
; Number of Swept Nodes Reported in Synthesis Report                         ; 5000               ; 5000               ;
; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
; Clock MUX Protection                                                       ; On                 ; On                 ;
; Auto Gated Clock Conversion                                                ; Off                ; Off                ;
; Block Design Naming                                                        ; Auto               ; Auto               ;
; SDC constraint protection                                                  ; Off                ; Off                ;
; Synthesis Effort                                                           ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
; Pre-Mapping Resynthesis Optimization                                       ; Off                ; Off                ;
; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
; Resource Aware Inference For Block RAM                                     ; On                 ; On                 ;
; Synthesis Seed                                                             ; 1                  ; 1                  ;
+----------------------------------------------------------------------------+--------------------+--------------------+


Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation                ;
+----------------------------+--------+
; Processors                 ; Number ;
+----------------------------+--------+
; Number detected on machine ; 4      ;
; Maximum allowed            ; 1      ;
+----------------------------+--------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                               ;
+----------------------------------------+-----------------+------------------------+------------------------------------------------------------------------+---------+
; File Name with User-Entered Path       ; Used in Netlist ; File Type              ; File Name with Absolute Path                                           ; Library ;
+----------------------------------------+-----------------+------------------------+------------------------------------------------------------------------+---------+
; ../../../rtl/verilog/wiegand_tx_top.v  ; yes             ; User Verilog HDL File  ; C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/wiegand_tx_top.v  ;         ;
; ../../../rtl/verilog/wiegand_defines.v ; yes             ; User Verilog HDL File  ; C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/wiegand_defines.v ;         ;
; ../../../rtl/verilog/wb_interface.v    ; yes             ; User Verilog HDL File  ; C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/wb_interface.v    ;         ;
; ../../../rtl/verilog/fifos.v           ; yes             ; User Verilog HDL File  ; C:/Users/jeffA/Desktop/rtl/wiegand/trunk/rtl/verilog/fifos.v           ;         ;
+----------------------------------------+-----------------+------------------------+------------------------------------------------------------------------+---------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+--------------------------+------------------+
; Resource                 ; Usage            ;
+--------------------------+------------------+
; I/O pins                 ; 87               ;
; DSP block 9-bit elements ; 0                ;
; Maximum fan-out node     ; wb_clk_i~input   ;
; Maximum fan-out          ; 303              ;
; Total fan-out            ; 2143             ;
; Average fan-out          ; 2.98             ;
+--------------------------+------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                             ;
+----------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+-------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node             ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                             ; Library Name ;
+----------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+-------------------------------------------------------------------------------------------------+--------------+
; |wiegand_tx_top                        ; 242 (142)         ; 303 (93)     ; 0           ; 0            ; 0       ; 0         ; 0         ; 87   ; 0            ; |wiegand_tx_top                                                                                 ; work         ;
;    |fifo_wieg:datafifowrite|           ; 43 (0)            ; 134 (0)      ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |wiegand_tx_top|fifo_wieg:datafifowrite                                                         ; work         ;
;       |custom_fifo_dp:custom_fifo_dp5| ; 19 (19)           ; 38 (14)      ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |wiegand_tx_top|fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp5                          ; work         ;
;          |mem_byte:mem[0].mem_byte|    ; 0 (0)             ; 8 (8)        ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |wiegand_tx_top|fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp5|mem_byte:mem[0].mem_byte ; work         ;
;          |mem_byte:mem[1].mem_byte|    ; 0 (0)             ; 8 (8)        ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |wiegand_tx_top|fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp5|mem_byte:mem[1].mem_byte ; work         ;
;          |mem_byte:mem[2].mem_byte|    ; 0 (0)             ; 8 (8)        ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |wiegand_tx_top|fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp5|mem_byte:mem[2].mem_byte ; work         ;
;       |custom_fifo_dp:custom_fifo_dp6| ; 8 (8)             ; 32 (8)       ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |wiegand_tx_top|fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp6                          ; work         ;
;          |mem_byte:mem[0].mem_byte|    ; 0 (0)             ; 8 (8)        ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |wiegand_tx_top|fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp6|mem_byte:mem[0].mem_byte ; work         ;
;          |mem_byte:mem[1].mem_byte|    ; 0 (0)             ; 8 (8)        ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |wiegand_tx_top|fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp6|mem_byte:mem[1].mem_byte ; work         ;
;          |mem_byte:mem[2].mem_byte|    ; 0 (0)             ; 8 (8)        ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |wiegand_tx_top|fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp6|mem_byte:mem[2].mem_byte ; work         ;
;       |custom_fifo_dp:custom_fifo_dp7| ; 8 (8)             ; 32 (8)       ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |wiegand_tx_top|fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp7                          ; work         ;
;          |mem_byte:mem[0].mem_byte|    ; 0 (0)             ; 8 (8)        ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |wiegand_tx_top|fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp7|mem_byte:mem[0].mem_byte ; work         ;
;          |mem_byte:mem[1].mem_byte|    ; 0 (0)             ; 8 (8)        ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |wiegand_tx_top|fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp7|mem_byte:mem[1].mem_byte ; work         ;
;          |mem_byte:mem[2].mem_byte|    ; 0 (0)             ; 8 (8)        ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |wiegand_tx_top|fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp7|mem_byte:mem[2].mem_byte ; work         ;
;       |custom_fifo_dp:custom_fifo_dp8| ; 8 (8)             ; 32 (8)       ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |wiegand_tx_top|fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp8                          ; work         ;
;          |mem_byte:mem[0].mem_byte|    ; 0 (0)             ; 8 (8)        ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |wiegand_tx_top|fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp8|mem_byte:mem[0].mem_byte ; work         ;
;          |mem_byte:mem[1].mem_byte|    ; 0 (0)             ; 8 (8)        ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |wiegand_tx_top|fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp8|mem_byte:mem[1].mem_byte ; work         ;
;          |mem_byte:mem[2].mem_byte|    ; 0 (0)             ; 8 (8)        ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |wiegand_tx_top|fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp8|mem_byte:mem[2].mem_byte ; work         ;
;    |wb_interface_wieg:wb_interface|    ; 57 (57)           ; 76 (76)      ; 0           ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |wiegand_tx_top|wb_interface_wieg:wb_interface                                                  ; work         ;
+----------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+-------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------+
; State Machine - |wiegand_tx_top|state                                             ;
+-----------+-----------+-----------+-----------+-----------+-----------+-----------+
; Name      ; state.111 ; state.110 ; state.101 ; state.100 ; state.001 ; state.000 ;
+-----------+-----------+-----------+-----------+-----------+-----------+-----------+
; state.000 ; 0         ; 0         ; 0         ; 0         ; 0         ; 0         ;
; state.001 ; 0         ; 0         ; 0         ; 0         ; 1         ; 1         ;
; state.100 ; 0         ; 0         ; 0         ; 1         ; 0         ; 1         ;
; state.101 ; 0         ; 0         ; 1         ; 0         ; 0         ; 1         ;
; state.110 ; 0         ; 1         ; 0         ; 0         ; 0         ; 1         ;
; state.111 ; 1         ; 0         ; 0         ; 0         ; 0         ; 1         ;
+-----------+-----------+-----------+-----------+-----------+-----------+-----------+


+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                                                                                                ;
+-------------------------------------------------------------------+-------------------------------------------------------------------------------+
; Register name                                                     ; Reason for Removal                                                            ;
+-------------------------------------------------------------------+-------------------------------------------------------------------------------+
; fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp6|addr_wr[2] ; Merged with fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp5|addr_wr[2] ;
; fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp7|addr_wr[2] ; Merged with fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp5|addr_wr[2] ;
; fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp8|addr_wr[2] ; Merged with fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp5|addr_wr[2] ;
; fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp6|addr_rd[0] ; Merged with fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp5|addr_rd[0] ;
; fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp7|addr_rd[0] ; Merged with fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp5|addr_rd[0] ;
; fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp8|addr_rd[0] ; Merged with fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp5|addr_rd[0] ;
; fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp6|addr_wr[0] ; Merged with fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp5|addr_wr[0] ;
; fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp7|addr_wr[0] ; Merged with fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp5|addr_wr[0] ;
; fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp8|addr_wr[0] ; Merged with fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp5|addr_wr[0] ;
; fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp6|addr_rd[1] ; Merged with fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp5|addr_rd[1] ;
; fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp7|addr_rd[1] ; Merged with fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp5|addr_rd[1] ;
; fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp8|addr_rd[1] ; Merged with fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp5|addr_rd[1] ;
; fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp6|addr_wr[1] ; Merged with fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp5|addr_wr[1] ;
; fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp7|addr_wr[1] ; Merged with fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp5|addr_wr[1] ;
; fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp8|addr_wr[1] ; Merged with fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp5|addr_wr[1] ;
; fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp6|addr_rd[2] ; Merged with fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp5|addr_rd[2] ;
; fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp7|addr_rd[2] ; Merged with fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp5|addr_rd[2] ;
; fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp8|addr_rd[2] ; Merged with fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp5|addr_rd[2] ;
; state~4                                                           ; Lost fanout                                                                   ;
; state~5                                                           ; Lost fanout                                                                   ;
; state~6                                                           ; Lost fanout                                                                   ;
; Total Number of Removed Registers = 21                            ;                                                                               ;
+-------------------------------------------------------------------+-------------------------------------------------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 303   ;
; Number of registers using Synchronous Clear  ; 51    ;
; Number of registers using Synchronous Load   ; 33    ;
; Number of registers using Asynchronous Clear ; 303   ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 218   ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-----------------------------------------------------------------------------+
; Inverted Register Statistics                                                ;
+-------------------------------------------------------------------+---------+
; Inverted Register                                                 ; Fan out ;
+-------------------------------------------------------------------+---------+
; one_o~reg0                                                        ; 2       ;
; zero_o~reg0                                                       ; 2       ;
; wb_interface_wieg:wb_interface|pulsewidth[1]                      ; 2       ;
; wb_interface_wieg:wb_interface|pulsewidth[3]                      ; 2       ;
; fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp5|addr_rd[0] ; 35      ;
; fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp5|addr_wr[0] ; 35      ;
; Total number of inverted registers = 6                            ;         ;
+-------------------------------------------------------------------+---------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                                                   ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                                                         ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------+
; 3:1                ; 7 bits    ; 14 LEs        ; 7 LEs                ; 7 LEs                  ; Yes        ; |wiegand_tx_top|bitCount[4]                                                        ;
; 3:1                ; 7 bits    ; 14 LEs        ; 7 LEs                ; 7 LEs                  ; Yes        ; |wiegand_tx_top|bitCountReg[3]                                                     ;
; 3:1                ; 31 bits   ; 62 LEs        ; 31 LEs               ; 31 LEs                 ; Yes        ; |wiegand_tx_top|word_out[21]                                                       ;
; 3:1                ; 32 bits   ; 64 LEs        ; 64 LEs               ; 0 LEs                  ; Yes        ; |wiegand_tx_top|fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp5|fifo_out[1] ;
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; No         ; |wiegand_tx_top|next_state                                                         ;
; 3:1                ; 23 bits   ; 46 LEs        ; 46 LEs               ; 0 LEs                  ; No         ; |wiegand_tx_top|wb_interface_wieg:wb_interface|wb_dat_rdbk[20]                     ;
; 3:1                ; 9 bits    ; 18 LEs        ; 18 LEs               ; 0 LEs                  ; No         ; |wiegand_tx_top|wb_interface_wieg:wb_interface|wb_dat_rdbk[5]                      ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "fifo_wieg:datafifowrite"                                                             ;
+-------+--------+----------+-------------------------------------------------------------------------------------+
; Port  ; Type   ; Severity ; Details                                                                             ;
+-------+--------+----------+-------------------------------------------------------------------------------------+
; empty ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+-------+--------+----------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------+
; Post-Synthesis Netlist Statistics for Top Partition ;
+-----------------------+-----------------------------+
; Type                  ; Count                       ;
+-----------------------+-----------------------------+
; boundary_port         ; 87                          ;
; cycloneiii_ff         ; 303                         ;
;     CLR               ; 15                          ;
;     CLR SCLR          ; 37                          ;
;     CLR SLD           ; 33                          ;
;     ENA CLR           ; 204                         ;
;     ENA CLR SCLR      ; 14                          ;
; cycloneiii_io_obuf    ; 32                          ;
; cycloneiii_lcell_comb ; 244                         ;
;     arith             ; 47                          ;
;         2 data inputs ; 47                          ;
;     normal            ; 197                         ;
;         1 data inputs ; 12                          ;
;         2 data inputs ; 12                          ;
;         3 data inputs ; 77                          ;
;         4 data inputs ; 96                          ;
;                       ;                             ;
; Max LUT depth         ; 4.10                        ;
; Average LUT depth     ; 2.13                        ;
+-----------------------+-----------------------------+


+-------------------------------+
; Elapsed Time Per Partition    ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top            ; 00:00:01     ;
+----------------+--------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit Analysis & Synthesis
    Info: Version 14.0.0 Build 200 06/17/2014 SJ Web Edition
    Info: Processing started: Mon Feb 16 10:59:27 2015
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off wiegand_tx_top -c wiegand_tx_top
Warning (20028): Parallel compilation is not licensed and has been disabled
Warning (10463): Verilog HDL Declaration warning at wiegand_tx_top.v(110): "bit" is SystemVerilog-2005 keyword
Info (12021): Found 1 design units, including 1 entities, in source file /users/jeffa/desktop/rtl/wiegand/trunk/rtl/verilog/wiegand_tx_top.v
    Info (12023): Found entity 1: wiegand_tx_top
Info (12021): Found 0 design units, including 0 entities, in source file /users/jeffa/desktop/rtl/wiegand/trunk/rtl/verilog/wiegand_defines.v
Info (12021): Found 1 design units, including 1 entities, in source file /users/jeffa/desktop/rtl/wiegand/trunk/rtl/verilog/wb_interface.v
    Info (12023): Found entity 1: wb_interface_wieg
Info (12021): Found 3 design units, including 3 entities, in source file /users/jeffa/desktop/rtl/wiegand/trunk/rtl/verilog/fifos.v
    Info (12023): Found entity 1: fifo_wieg
    Info (12023): Found entity 2: custom_fifo_dp
    Info (12023): Found entity 3: mem_byte
Warning (10236): Verilog HDL Implicit Net warning at wiegand_tx_top.v(235): created implicit net for "wb_wr_en"
Warning (10236): Verilog HDL Implicit Net warning at wiegand_tx_top.v(235): created implicit net for "empty"
Info (12127): Elaborating entity "wiegand_tx_top" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at wiegand_tx_top.v(141): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at wiegand_tx_top.v(155): truncated value with size 32 to match size of target (7)
Warning (10230): Verilog HDL assignment warning at wiegand_tx_top.v(161): truncated value with size 32 to match size of target (7)
Info (12128): Elaborating entity "fifo_wieg" for hierarchy "fifo_wieg:datafifowrite"
Info (12128): Elaborating entity "custom_fifo_dp" for hierarchy "fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp5"
Info (12128): Elaborating entity "mem_byte" for hierarchy "fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp5|mem_byte:mem[0].mem_byte"
Info (12128): Elaborating entity "wb_interface_wieg" for hierarchy "wb_interface_wieg:wb_interface"
Warning (10230): Verilog HDL assignment warning at wb_interface.v(144): truncated value with size 6 to match size of target (1)
Warning (13046): Tri-state node(s) do not directly drive top-level pin(s)
    Warning (13048): Converted tri-state node "fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp8|mem_byte_out[7]" into a selector
    Warning (13048): Converted tri-state node "fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp8|mem_byte_out[6]" into a selector
    Warning (13048): Converted tri-state node "fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp8|mem_byte_out[5]" into a selector
    Warning (13048): Converted tri-state node "fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp8|mem_byte_out[4]" into a selector
    Warning (13048): Converted tri-state node "fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp8|mem_byte_out[3]" into a selector
    Warning (13048): Converted tri-state node "fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp8|mem_byte_out[2]" into a selector
    Warning (13048): Converted tri-state node "fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp8|mem_byte_out[1]" into a selector
    Warning (13048): Converted tri-state node "fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp8|mem_byte_out[0]" into a selector
    Warning (13048): Converted tri-state node "fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp7|mem_byte_out[7]" into a selector
    Warning (13048): Converted tri-state node "fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp7|mem_byte_out[6]" into a selector
    Warning (13048): Converted tri-state node "fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp7|mem_byte_out[5]" into a selector
    Warning (13048): Converted tri-state node "fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp7|mem_byte_out[4]" into a selector
    Warning (13048): Converted tri-state node "fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp7|mem_byte_out[3]" into a selector
    Warning (13048): Converted tri-state node "fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp7|mem_byte_out[2]" into a selector
    Warning (13048): Converted tri-state node "fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp7|mem_byte_out[1]" into a selector
    Warning (13048): Converted tri-state node "fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp7|mem_byte_out[0]" into a selector
    Warning (13048): Converted tri-state node "fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp6|mem_byte_out[7]" into a selector
    Warning (13048): Converted tri-state node "fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp6|mem_byte_out[6]" into a selector
    Warning (13048): Converted tri-state node "fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp6|mem_byte_out[5]" into a selector
    Warning (13048): Converted tri-state node "fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp6|mem_byte_out[4]" into a selector
    Warning (13048): Converted tri-state node "fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp6|mem_byte_out[3]" into a selector
    Warning (13048): Converted tri-state node "fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp6|mem_byte_out[2]" into a selector
    Warning (13048): Converted tri-state node "fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp6|mem_byte_out[1]" into a selector
    Warning (13048): Converted tri-state node "fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp6|mem_byte_out[0]" into a selector
    Warning (13048): Converted tri-state node "fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp5|mem_byte_out[7]" into a selector
    Warning (13048): Converted tri-state node "fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp5|mem_byte_out[6]" into a selector
    Warning (13048): Converted tri-state node "fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp5|mem_byte_out[5]" into a selector
    Warning (13048): Converted tri-state node "fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp5|mem_byte_out[4]" into a selector
    Warning (13048): Converted tri-state node "fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp5|mem_byte_out[3]" into a selector
    Warning (13048): Converted tri-state node "fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp5|mem_byte_out[2]" into a selector
    Warning (13048): Converted tri-state node "fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp5|mem_byte_out[1]" into a selector
    Warning (13048): Converted tri-state node "fifo_wieg:datafifowrite|custom_fifo_dp:custom_fifo_dp5|mem_byte_out[0]" into a selector
Info (13000): Registers with preset signals will power-up high
Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Info (286030): Timing-Driven Synthesis is running
Info (17049): 3 registers lost all their fanouts during netlist optimizations.
Info (144001): Generated suppressed messages file C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/altera/wiegand_tx/output_files/wiegand_tx_top.map.smsg
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
Warning (21074): Design contains 7 input pin(s) that do not drive logic
    Warning (15610): No output dependent on input pin "wb_cti_i[0]"
    Warning (15610): No output dependent on input pin "wb_cti_i[1]"
    Warning (15610): No output dependent on input pin "wb_cti_i[2]"
    Warning (15610): No output dependent on input pin "wb_sel_i[0]"
    Warning (15610): No output dependent on input pin "wb_sel_i[1]"
    Warning (15610): No output dependent on input pin "wb_sel_i[2]"
    Warning (15610): No output dependent on input pin "wb_sel_i[3]"
Info (21057): Implemented 498 device resources after synthesis - the final resource count might be different
    Info (21058): Implemented 50 input pins
    Info (21059): Implemented 37 output pins
    Info (21061): Implemented 411 logic cells
Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 49 warnings
    Info: Peak virtual memory: 583 megabytes
    Info: Processing ended: Mon Feb 16 10:59:31 2015
    Info: Elapsed time: 00:00:04
    Info: Total CPU time (on all processors): 00:00:03


+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/altera/wiegand_tx/output_files/wiegand_tx_top.map.smsg.


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