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[/] [wiegand_ctl/] [trunk/] [syn/] [xilinx/] [wiegand_tx/] [ise/] [wiegand_tx_top/] [wiegand_tx_top.pcf] - Rev 17
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//! **************************************************************************// Written by: Map P.20131013 on Mon Feb 16 11:08:35 2015//! **************************************************************************SCHEMATIC START;COMP "one_o" LOCATE = SITE "A2" LEVEL 1;COMP "zero_o" LOCATE = SITE "A3" LEVEL 1;TIMEGRP wb_clk_i = BEL "lock_cfg" BEL "full_dly" BEL "one_o" BEL "zero_o" BEL"word_out_0" BEL "word_out_1" BEL "word_out_2" BEL "word_out_3" BEL"word_out_4" BEL "word_out_5" BEL "word_out_6" BEL "word_out_7" BEL"word_out_8" BEL "word_out_9" BEL "word_out_10" BEL "word_out_11" BEL"word_out_12" BEL "word_out_13" BEL "word_out_14" BEL "word_out_15"BEL "word_out_16" BEL "word_out_17" BEL "word_out_18" BEL"word_out_19" BEL "word_out_20" BEL "word_out_21" BEL "word_out_22"BEL "word_out_23" BEL "word_out_24" BEL "word_out_25" BEL"word_out_26" BEL "word_out_27" BEL "word_out_28" BEL "word_out_29"BEL "word_out_30" BEL "word_out_31" BEL "p2pCnt_0" BEL "p2pCnt_1" BEL"p2pCnt_2" BEL "p2pCnt_3" BEL "p2pCnt_4" BEL "pulseCnt_0" BEL"pulseCnt_1" BEL "pulseCnt_2" BEL "pulseCnt_3" BEL "pulseCnt_4" BEL"pulseCnt_5" BEL "pulseCnt_6" BEL "pulseCnt_7" BEL "pulseCnt_8" BEL"pulseCnt_9" BEL "pulseCnt_10" BEL "pulseCnt_11" BEL "pulseCnt_12" BEL"pulseCnt_13" BEL "pulseCnt_14" BEL "pulseCnt_15" BEL "pulseCnt_16"BEL "pulseCnt_17" BEL "pulseCnt_18" BEL "pulseCnt_19" BEL"pulseCnt_20" BEL "pulseCnt_21" BEL "pulseCnt_22" BEL "pulseCnt_23"BEL "pulseCnt_24" BEL "pulseCnt_25" BEL "pulseCnt_26" BEL"pulseCnt_27" BEL "pulseCnt_28" BEL "pulseCnt_29" BEL "pulseCnt_30"BEL "pulseCnt_31" BEL "bitCount_0" BEL "bitCount_1" BEL "bitCount_2"BEL "bitCount_3" BEL "bitCount_4" BEL "bitCount_5" BEL "bitCount_6"BEL "bitCountReg_0" BEL "bitCountReg_1" BEL "bitCountReg_2" BEL"bitCountReg_3" BEL "bitCountReg_4" BEL "bitCountReg_5" BEL"bitCountReg_6" BEL "state_FSM_FFd3" BEL "state_FSM_FFd1" BEL"state_FSM_FFd2" BEL "wb_interface/pulsewidth_0" BEL"wb_interface/pulsewidth_1" BEL "wb_interface/pulsewidth_2" BEL"wb_interface/pulsewidth_3" BEL "wb_interface/pulsewidth_4" BEL"wb_interface/pulsewidth_5" BEL "wb_interface/pulsewidth_6" BEL"wb_interface/pulsewidth_7" BEL "wb_interface/pulsewidth_8" BEL"wb_interface/pulsewidth_9" BEL "wb_interface/pulsewidth_10" BEL"wb_interface/pulsewidth_11" BEL "wb_interface/pulsewidth_12" BEL"wb_interface/pulsewidth_13" BEL "wb_interface/pulsewidth_14" BEL"wb_interface/pulsewidth_15" BEL "wb_interface/pulsewidth_16" BEL"wb_interface/pulsewidth_17" BEL "wb_interface/pulsewidth_18" BEL"wb_interface/pulsewidth_19" BEL "wb_interface/pulsewidth_20" BEL"wb_interface/pulsewidth_21" BEL "wb_interface/pulsewidth_22" BEL"wb_interface/pulsewidth_23" BEL "wb_interface/pulsewidth_24" BEL"wb_interface/pulsewidth_25" BEL "wb_interface/pulsewidth_26" BEL"wb_interface/pulsewidth_27" BEL "wb_interface/pulsewidth_28" BEL"wb_interface/pulsewidth_29" BEL "wb_interface/pulsewidth_30" BEL"wb_interface/pulsewidth_31" BEL "wb_interface/size_8" BEL"wb_interface/size_7" BEL "wb_interface/p2p_31" BEL"wb_interface/p2p_30" BEL "wb_interface/p2p_29" BEL"wb_interface/p2p_28" BEL "wb_interface/p2p_27" BEL"wb_interface/p2p_26" BEL "wb_interface/p2p_25" BEL"wb_interface/p2p_24" BEL "wb_interface/p2p_23" BEL"wb_interface/p2p_22" BEL "wb_interface/p2p_21" BEL"wb_interface/p2p_20" BEL "wb_interface/p2p_19" BEL"wb_interface/p2p_18" BEL "wb_interface/p2p_17" BEL"wb_interface/p2p_16" BEL "wb_interface/p2p_15" BEL"wb_interface/p2p_14" BEL "wb_interface/p2p_13" BEL"wb_interface/p2p_12" BEL "wb_interface/p2p_11" BEL"wb_interface/p2p_10" BEL "wb_interface/p2p_9" BEL"wb_interface/p2p_8" BEL "wb_interface/p2p_7" BEL "wb_interface/p2p_6"BEL "wb_interface/p2p_5" BEL "wb_interface/p2p_4" BEL"wb_interface/p2p_3" BEL "wb_interface/p2p_2" BEL "wb_interface/p2p_1"BEL "wb_interface/p2p_0" BEL "wb_interface/rty" BEL "wb_interface/err"BEL "wb_interface/ack" BEL"datafifowrite/custom_fifo_dp5/mem[0].mem_byte/byte_reg_0" BEL"datafifowrite/custom_fifo_dp5/mem[0].mem_byte/byte_reg_1" BEL"datafifowrite/custom_fifo_dp5/mem[0].mem_byte/byte_reg_2" BEL"datafifowrite/custom_fifo_dp5/mem[0].mem_byte/byte_reg_3" BEL"datafifowrite/custom_fifo_dp5/mem[0].mem_byte/byte_reg_4" BEL"datafifowrite/custom_fifo_dp5/mem[0].mem_byte/byte_reg_5" BEL"datafifowrite/custom_fifo_dp5/mem[0].mem_byte/byte_reg_6" BEL"datafifowrite/custom_fifo_dp5/mem[0].mem_byte/byte_reg_7" BEL"datafifowrite/custom_fifo_dp5/mem[1].mem_byte/byte_reg_0" BEL"datafifowrite/custom_fifo_dp5/mem[1].mem_byte/byte_reg_1" BEL"datafifowrite/custom_fifo_dp5/mem[1].mem_byte/byte_reg_2" BEL"datafifowrite/custom_fifo_dp5/mem[1].mem_byte/byte_reg_3" BEL"datafifowrite/custom_fifo_dp5/mem[1].mem_byte/byte_reg_4" BEL"datafifowrite/custom_fifo_dp5/mem[1].mem_byte/byte_reg_5" BEL"datafifowrite/custom_fifo_dp5/mem[1].mem_byte/byte_reg_6" BEL"datafifowrite/custom_fifo_dp5/mem[1].mem_byte/byte_reg_7" BEL"datafifowrite/custom_fifo_dp5/mem[2].mem_byte/byte_reg_0" BEL"datafifowrite/custom_fifo_dp5/mem[2].mem_byte/byte_reg_1" BEL"datafifowrite/custom_fifo_dp5/mem[2].mem_byte/byte_reg_2" BEL"datafifowrite/custom_fifo_dp5/mem[2].mem_byte/byte_reg_3" BEL"datafifowrite/custom_fifo_dp5/mem[2].mem_byte/byte_reg_4" BEL"datafifowrite/custom_fifo_dp5/mem[2].mem_byte/byte_reg_5" BEL"datafifowrite/custom_fifo_dp5/mem[2].mem_byte/byte_reg_6" BEL"datafifowrite/custom_fifo_dp5/mem[2].mem_byte/byte_reg_7" BEL"datafifowrite/custom_fifo_dp5/fifo_out_7" BEL"datafifowrite/custom_fifo_dp5/fifo_out_6" BEL"datafifowrite/custom_fifo_dp5/fifo_out_5" BEL"datafifowrite/custom_fifo_dp5/fifo_out_4" BEL"datafifowrite/custom_fifo_dp5/fifo_out_3" BEL"datafifowrite/custom_fifo_dp5/fifo_out_2" BEL"datafifowrite/custom_fifo_dp5/fifo_out_1" BEL"datafifowrite/custom_fifo_dp5/fifo_out_0" BEL"datafifowrite/custom_fifo_dp5/addr_rd_0" BEL"datafifowrite/custom_fifo_dp5/addr_wr_0" BEL"datafifowrite/custom_fifo_dp5/addr_rd_2" BEL"datafifowrite/custom_fifo_dp5/addr_wr_2" BEL"datafifowrite/custom_fifo_dp5/addr_rd_1" BEL"datafifowrite/custom_fifo_dp5/addr_wr_1" BEL"datafifowrite/custom_fifo_dp6/mem[0].mem_byte/byte_reg_0" BEL"datafifowrite/custom_fifo_dp6/mem[0].mem_byte/byte_reg_1" BEL"datafifowrite/custom_fifo_dp6/mem[0].mem_byte/byte_reg_2" BEL"datafifowrite/custom_fifo_dp6/mem[0].mem_byte/byte_reg_3" BEL"datafifowrite/custom_fifo_dp6/mem[0].mem_byte/byte_reg_4" BEL"datafifowrite/custom_fifo_dp6/mem[0].mem_byte/byte_reg_5" BEL"datafifowrite/custom_fifo_dp6/mem[0].mem_byte/byte_reg_6" BEL"datafifowrite/custom_fifo_dp6/mem[0].mem_byte/byte_reg_7" BEL"datafifowrite/custom_fifo_dp6/mem[1].mem_byte/byte_reg_0" BEL"datafifowrite/custom_fifo_dp6/mem[1].mem_byte/byte_reg_1" BEL"datafifowrite/custom_fifo_dp6/mem[1].mem_byte/byte_reg_2" BEL"datafifowrite/custom_fifo_dp6/mem[1].mem_byte/byte_reg_3" BEL"datafifowrite/custom_fifo_dp6/mem[1].mem_byte/byte_reg_4" BEL"datafifowrite/custom_fifo_dp6/mem[1].mem_byte/byte_reg_5" BEL"datafifowrite/custom_fifo_dp6/mem[1].mem_byte/byte_reg_6" BEL"datafifowrite/custom_fifo_dp6/mem[1].mem_byte/byte_reg_7" BEL"datafifowrite/custom_fifo_dp6/mem[2].mem_byte/byte_reg_0" BEL"datafifowrite/custom_fifo_dp6/mem[2].mem_byte/byte_reg_1" BEL"datafifowrite/custom_fifo_dp6/mem[2].mem_byte/byte_reg_2" BEL"datafifowrite/custom_fifo_dp6/mem[2].mem_byte/byte_reg_3" BEL"datafifowrite/custom_fifo_dp6/mem[2].mem_byte/byte_reg_4" BEL"datafifowrite/custom_fifo_dp6/mem[2].mem_byte/byte_reg_5" BEL"datafifowrite/custom_fifo_dp6/mem[2].mem_byte/byte_reg_6" BEL"datafifowrite/custom_fifo_dp6/mem[2].mem_byte/byte_reg_7" BEL"datafifowrite/custom_fifo_dp6/fifo_out_7" BEL"datafifowrite/custom_fifo_dp6/fifo_out_6" BEL"datafifowrite/custom_fifo_dp6/fifo_out_5" BEL"datafifowrite/custom_fifo_dp6/fifo_out_4" BEL"datafifowrite/custom_fifo_dp6/fifo_out_3" BEL"datafifowrite/custom_fifo_dp6/fifo_out_2" BEL"datafifowrite/custom_fifo_dp6/fifo_out_1" BEL"datafifowrite/custom_fifo_dp6/fifo_out_0" BEL"datafifowrite/custom_fifo_dp6/addr_rd_0" BEL"datafifowrite/custom_fifo_dp6/addr_wr_0" BEL"datafifowrite/custom_fifo_dp6/addr_rd_2" BEL"datafifowrite/custom_fifo_dp6/addr_wr_2" BEL"datafifowrite/custom_fifo_dp6/addr_rd_1" BEL"datafifowrite/custom_fifo_dp6/addr_wr_1" BEL"datafifowrite/custom_fifo_dp7/mem[0].mem_byte/byte_reg_0" BEL"datafifowrite/custom_fifo_dp7/mem[0].mem_byte/byte_reg_1" BEL"datafifowrite/custom_fifo_dp7/mem[0].mem_byte/byte_reg_2" BEL"datafifowrite/custom_fifo_dp7/mem[0].mem_byte/byte_reg_3" BEL"datafifowrite/custom_fifo_dp7/mem[0].mem_byte/byte_reg_4" BEL"datafifowrite/custom_fifo_dp7/mem[0].mem_byte/byte_reg_5" BEL"datafifowrite/custom_fifo_dp7/mem[0].mem_byte/byte_reg_6" BEL"datafifowrite/custom_fifo_dp7/mem[0].mem_byte/byte_reg_7" BEL"datafifowrite/custom_fifo_dp7/mem[1].mem_byte/byte_reg_0" BEL"datafifowrite/custom_fifo_dp7/mem[1].mem_byte/byte_reg_1" BEL"datafifowrite/custom_fifo_dp7/mem[1].mem_byte/byte_reg_2" BEL"datafifowrite/custom_fifo_dp7/mem[1].mem_byte/byte_reg_3" BEL"datafifowrite/custom_fifo_dp7/mem[1].mem_byte/byte_reg_4" BEL"datafifowrite/custom_fifo_dp7/mem[1].mem_byte/byte_reg_5" BEL"datafifowrite/custom_fifo_dp7/mem[1].mem_byte/byte_reg_6" BEL"datafifowrite/custom_fifo_dp7/mem[1].mem_byte/byte_reg_7" BEL"datafifowrite/custom_fifo_dp7/mem[2].mem_byte/byte_reg_0" BEL"datafifowrite/custom_fifo_dp7/mem[2].mem_byte/byte_reg_1" BEL"datafifowrite/custom_fifo_dp7/mem[2].mem_byte/byte_reg_2" BEL"datafifowrite/custom_fifo_dp7/mem[2].mem_byte/byte_reg_3" BEL"datafifowrite/custom_fifo_dp7/mem[2].mem_byte/byte_reg_4" BEL"datafifowrite/custom_fifo_dp7/mem[2].mem_byte/byte_reg_5" BEL"datafifowrite/custom_fifo_dp7/mem[2].mem_byte/byte_reg_6" BEL"datafifowrite/custom_fifo_dp7/mem[2].mem_byte/byte_reg_7" BEL"datafifowrite/custom_fifo_dp7/fifo_out_7" BEL"datafifowrite/custom_fifo_dp7/fifo_out_6" BEL"datafifowrite/custom_fifo_dp7/fifo_out_5" BEL"datafifowrite/custom_fifo_dp7/fifo_out_4" BEL"datafifowrite/custom_fifo_dp7/fifo_out_3" BEL"datafifowrite/custom_fifo_dp7/fifo_out_2" BEL"datafifowrite/custom_fifo_dp7/fifo_out_1" BEL"datafifowrite/custom_fifo_dp7/fifo_out_0" BEL"datafifowrite/custom_fifo_dp7/addr_rd_0" BEL"datafifowrite/custom_fifo_dp7/addr_wr_0" BEL"datafifowrite/custom_fifo_dp7/addr_rd_2" BEL"datafifowrite/custom_fifo_dp7/addr_wr_2" BEL"datafifowrite/custom_fifo_dp7/addr_rd_1" BEL"datafifowrite/custom_fifo_dp7/addr_wr_1" BEL"datafifowrite/custom_fifo_dp8/mem[0].mem_byte/byte_reg_0" BEL"datafifowrite/custom_fifo_dp8/mem[0].mem_byte/byte_reg_1" BEL"datafifowrite/custom_fifo_dp8/mem[0].mem_byte/byte_reg_2" BEL"datafifowrite/custom_fifo_dp8/mem[0].mem_byte/byte_reg_3" BEL"datafifowrite/custom_fifo_dp8/mem[0].mem_byte/byte_reg_4" BEL"datafifowrite/custom_fifo_dp8/mem[0].mem_byte/byte_reg_5" BEL"datafifowrite/custom_fifo_dp8/mem[0].mem_byte/byte_reg_6" BEL"datafifowrite/custom_fifo_dp8/mem[0].mem_byte/byte_reg_7" BEL"datafifowrite/custom_fifo_dp8/mem[1].mem_byte/byte_reg_0" BEL"datafifowrite/custom_fifo_dp8/mem[1].mem_byte/byte_reg_1" BEL"datafifowrite/custom_fifo_dp8/mem[1].mem_byte/byte_reg_2" BEL"datafifowrite/custom_fifo_dp8/mem[1].mem_byte/byte_reg_3" BEL"datafifowrite/custom_fifo_dp8/mem[1].mem_byte/byte_reg_4" BEL"datafifowrite/custom_fifo_dp8/mem[1].mem_byte/byte_reg_5" BEL"datafifowrite/custom_fifo_dp8/mem[1].mem_byte/byte_reg_6" BEL"datafifowrite/custom_fifo_dp8/mem[1].mem_byte/byte_reg_7" BEL"datafifowrite/custom_fifo_dp8/mem[2].mem_byte/byte_reg_0" BEL"datafifowrite/custom_fifo_dp8/mem[2].mem_byte/byte_reg_1" BEL"datafifowrite/custom_fifo_dp8/mem[2].mem_byte/byte_reg_2" BEL"datafifowrite/custom_fifo_dp8/mem[2].mem_byte/byte_reg_3" BEL"datafifowrite/custom_fifo_dp8/mem[2].mem_byte/byte_reg_4" BEL"datafifowrite/custom_fifo_dp8/mem[2].mem_byte/byte_reg_5" BEL"datafifowrite/custom_fifo_dp8/mem[2].mem_byte/byte_reg_6" BEL"datafifowrite/custom_fifo_dp8/mem[2].mem_byte/byte_reg_7" BEL"datafifowrite/custom_fifo_dp8/fifo_out_7" BEL"datafifowrite/custom_fifo_dp8/fifo_out_6" BEL"datafifowrite/custom_fifo_dp8/fifo_out_5" BEL"datafifowrite/custom_fifo_dp8/fifo_out_4" BEL"datafifowrite/custom_fifo_dp8/fifo_out_3" BEL"datafifowrite/custom_fifo_dp8/fifo_out_2" BEL"datafifowrite/custom_fifo_dp8/fifo_out_1" BEL"datafifowrite/custom_fifo_dp8/fifo_out_0" BEL"datafifowrite/custom_fifo_dp8/addr_rd_0" BEL"datafifowrite/custom_fifo_dp8/addr_wr_0" BEL"datafifowrite/custom_fifo_dp8/addr_rd_2" BEL"datafifowrite/custom_fifo_dp8/addr_wr_2" BEL"datafifowrite/custom_fifo_dp8/addr_rd_1" BEL"datafifowrite/custom_fifo_dp8/addr_wr_1" BEL "wb_interface/size_6"BEL "wb_interface/size_5" BEL "wb_interface/size_4" BEL"wb_interface/size_3" BEL "wb_interface/size_2" BEL"wb_interface/size_1" BEL "wb_interface/size_0" BEL"wb_clk_i_BUFGP/BUFG.GCLKMUX" BEL "wb_clk_i_BUFGP/BUFG";TS_wb_clk_i = PERIOD TIMEGRP "wb_clk_i" 20 ns HIGH 50%;SCHEMATIC END;