Subversion Repositories wiegand_ctl

Release 14.7 Map P.20131013 (nt64)
Xilinx Map Application Log File for Design 'wiegand_tx_top'

Design Information
------------------
Command Line   : map -intstyle ise -p xc3s700an-fgg484-4 -cm area -ir off -pr
off -c 100 -o wiegand_tx_top_map.ncd wiegand_tx_top.ngd wiegand_tx_top.pcf 
Target Device  : xc3s700an
Target Package : fgg484
Target Speed   : -4
Mapper Version : spartan3a -- $Revision: 1.55 $
Mapped Date    : Mon Feb 16 11:08:32 2015

Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...
Updating timing models...

Design Summary
--------------

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:           318 out of  11,776    2%
  Number of 4 input LUTs:               305 out of  11,776    2%
Logic Distribution:
  Number of occupied Slices:            257 out of   5,888    4%
    Number of Slices containing only related logic:     257 out of     257 100%
    Number of Slices containing unrelated logic:          0 out of     257   0%
      *See NOTES below for an explanation of the effects of unrelated logic.
  Total Number of 4 input LUTs:         305 out of  11,776    2%
  Number of bonded IOBs:                 80 out of     372   21%
  Number of BUFGMUXs:                     1 out of      24    4%

Average Fanout of Non-Clock Nets:                3.79

Peak Memory Usage:  346 MB
Total REAL time to MAP completion:  3 secs 
Total CPU time to MAP completion:   2 secs 

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "wiegand_tx_top_map.mrp" for details.