URL
https://opencores.org/ocsvn/xenie/xenie/trunk
Subversion Repositories xenie
[/] [xenie/] [trunk/] [examples/] [Eth_example/] [src/] [constr/] [xenie_1_0.xdc] - Rev 4
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set_property PACKAGE_PIN D24 [get_ports I2C_SDA]set_property PACKAGE_PIN D25 [get_ports I2C_SCL]set_property IOSTANDARD LVCMOS33 [get_ports I2C_SCL]set_property IOSTANDARD LVCMOS33 [get_ports I2C_SDA]set_property PACKAGE_PIN D21 [get_ports ETH_MDIO_MDC]set_property PACKAGE_PIN A20 [get_ports ETH_MDIO_MDIO]set_property IOSTANDARD LVCMOS33 [get_ports ETH_MDIO_MDC]set_property IOSTANDARD LVCMOS33 [get_ports ETH_MDIO_MDIO]set_property PACKAGE_PIN F15 [get_ports MB_UART_TX]set_property PACKAGE_PIN J15 [get_ports MB_UART_RX]set_property IOSTANDARD LVCMOS33 [get_ports MB_UART_RX]set_property IOSTANDARD LVCMOS33 [get_ports MB_UART_TX]set_property PACKAGE_PIN B24 [get_ports {CFG_QSPI_IO[0]}]set_property PACKAGE_PIN A25 [get_ports {CFG_QSPI_IO[1]}]set_property PACKAGE_PIN B22 [get_ports {CFG_QSPI_IO[2]}]set_property PACKAGE_PIN A22 [get_ports {CFG_QSPI_IO[3]}]set_property PACKAGE_PIN C23 [get_ports CFG_QSPI_SS]set_property IOSTANDARD LVCMOS33 [get_ports {CFG_QSPI_IO[3]}]set_property IOSTANDARD LVCMOS33 [get_ports {CFG_QSPI_IO[2]}]set_property IOSTANDARD LVCMOS33 [get_ports {CFG_QSPI_IO[1]}]set_property IOSTANDARD LVCMOS33 [get_ports {CFG_QSPI_IO[0]}]set_property IOSTANDARD LVCMOS33 [get_ports CFG_QSPI_SS]set_property PACKAGE_PIN D26 [get_ports {LEDS[1]}]set_property PACKAGE_PIN E26 [get_ports {LEDS[0]}]set_property IOSTANDARD LVCMOS33 [get_ports {LEDS[1]}]set_property IOSTANDARD LVCMOS33 [get_ports {LEDS[0]}]set_property IOSTANDARD LVCMOS33 [get_ports {ETH_PHY_GPIO[5]}]set_property IOSTANDARD LVCMOS33 [get_ports {ETH_PHY_GPIO[4]}]set_property IOSTANDARD LVCMOS33 [get_ports {ETH_PHY_GPIO[3]}]set_property IOSTANDARD LVCMOS33 [get_ports {ETH_PHY_GPIO[2]}]set_property IOSTANDARD LVCMOS33 [get_ports {ETH_PHY_GPIO[1]}]set_property IOSTANDARD LVCMOS33 [get_ports {ETH_PHY_GPIO[0]}]set_property PACKAGE_PIN C26 [get_ports {ETH_PHY_GPIO[3]}]set_property PACKAGE_PIN A23 [get_ports {ETH_PHY_GPIO[4]}]set_property PACKAGE_PIN C22 [get_ports {ETH_PHY_GPIO[5]}]set_property PACKAGE_PIN E21 [get_ports ETH_PHY_CLK_SRC_SEL]set_property PACKAGE_PIN B21 [get_ports ETH_PHY_RESETN]set_property PACKAGE_PIN G24 [get_ports ETH_PHY_RCLK1]set_property PACKAGE_PIN B20 [get_ports ETH_PHY_INTN]set_property PACKAGE_PIN H26 [get_ports ALL_SRC_PG]set_property IOSTANDARD LVCMOS33 [get_ports ALL_SRC_PG]set_property IOSTANDARD LVCMOS33 [get_ports ETH_PHY_CLK_SRC_SEL]set_property IOSTANDARD LVCMOS33 [get_ports ETH_PHY_INTN]set_property IOSTANDARD LVCMOS33 [get_ports ETH_PHY_RCLK1]set_property IOSTANDARD LVCMOS33 [get_ports ETH_PHY_RESETN]set_property PACKAGE_PIN AB11 [get_ports CLK_200M_IN_P]set_property PACKAGE_PIN C24 [get_ports {ETH_PHY_GPIO[0]}]set_property PACKAGE_PIN A24 [get_ports {ETH_PHY_GPIO[1]}]set_property PACKAGE_PIN B26 [get_ports {ETH_PHY_GPIO[2]}]set_property PACKAGE_PIN R4 [get_ports {ETH_RXAUI_RX_P[0]}]set_property PACKAGE_PIN N4 [get_ports {ETH_RXAUI_RX_P[1]}]set_property IOSTANDARD DIFF_SSTL135 [get_ports CLK_200M_IN_P]set_property IOSTANDARD DIFF_SSTL135 [get_ports CLK_200M_IN_N]set_property PACKAGE_PIN H6 [get_ports ETH_RXAUI_REFCLK_P]set_property PACKAGE_PIN H5 [get_ports ETH_RXAUI_REFCLK_N]set_property PACKAGE_PIN H14 [get_ports {DBG_PORT[0]}]set_property PACKAGE_PIN G14 [get_ports {DBG_PORT[1]}]set_property PACKAGE_PIN F14 [get_ports {DBG_PORT[2]}]set_property PACKAGE_PIN F13 [get_ports {DBG_PORT[3]}]set_property PACKAGE_PIN D14 [get_ports {DBG_PORT[4]}]set_property PACKAGE_PIN D13 [get_ports {DBG_PORT[5]}]set_property PACKAGE_PIN B10 [get_ports {DBG_PORT[6]}]set_property PACKAGE_PIN A10 [get_ports {DBG_PORT[7]}]set_property IOSTANDARD LVCMOS33 [get_ports {DBG_PORT[0]}]set_property IOSTANDARD LVCMOS33 [get_ports {DBG_PORT[1]}]set_property IOSTANDARD LVCMOS33 [get_ports {DBG_PORT[2]}]set_property IOSTANDARD LVCMOS33 [get_ports {DBG_PORT[3]}]set_property IOSTANDARD LVCMOS33 [get_ports {DBG_PORT[4]}]set_property IOSTANDARD LVCMOS33 [get_ports {DBG_PORT[5]}]set_property IOSTANDARD LVCMOS33 [get_ports {DBG_PORT[6]}]set_property IOSTANDARD LVCMOS33 [get_ports {DBG_PORT[7]}]set_property PACKAGE_PIN F9 [get_ports {DBG_PORT[8]}]set_property PACKAGE_PIN F8 [get_ports {DBG_PORT[9]}]set_property PACKAGE_PIN G11 [get_ports {DBG_PORT[10]}]set_property PACKAGE_PIN F10 [get_ports {DBG_PORT[11]}]set_property PACKAGE_PIN J8 [get_ports {DBG_PORT[12]}]set_property IOSTANDARD LVCMOS33 [get_ports {DBG_PORT[8]}]set_property IOSTANDARD LVCMOS33 [get_ports {DBG_PORT[9]}]set_property IOSTANDARD LVCMOS33 [get_ports {DBG_PORT[10]}]set_property IOSTANDARD LVCMOS33 [get_ports {DBG_PORT[11]}]set_property IOSTANDARD LVCMOS33 [get_ports {DBG_PORT[12]}]create_clock -period 5.000 -name CLK_200M_IN_P -waveform {0.000 2.500} [get_ports CLK_200M_IN_P]set_clock_groups -asynchronous -group [get_clocks rxaui_inst/U0/rxaui_block_i/gt0_wrapper_i/gtxe2_i/TXOUTCLK]# Exclude reset of RXAUI core driven by MB GPIO from timing analysis#set_false_path -from [get_pins {main_bd_inst/axi_gpio_0/U0/gpio_core_1/Dual.gpio_Data_Out_reg[31]/C}]#set_false_path -from [get_pins {main_bd_inst/axi_gpio_2_netInfo/U0/gpio_core_1/Dual.gpio_OE_reg[*]/C}]set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]set_property BITSTREAM.CONFIG.OVERTEMPPOWERDOWN ENABLE [current_design]set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]