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[/] [xenie/] [trunk/] [examples/] [Eth_example/] [src/] [ip/] [rxaui_0/] [rxaui_0.xml] - Rev 4

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<?xml version="1.0" encoding="UTF-8"?>
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
  <spirit:vendor>xilinx.com</spirit:vendor>
  <spirit:library>customized_ip</spirit:library>
  <spirit:name>rxaui_0</spirit:name>
  <spirit:version>1.0</spirit:version>
  <spirit:busInterfaces>
    <spirit:busInterface>
      <spirit:name>mdio_interface</spirit:name>
      <spirit:displayName>mdio_interface</spirit:displayName>
      <spirit:description>mdio interface</spirit:description>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="mdio" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="mdio_rtl" spirit:version="1.0"/>
      <spirit:slave/>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>MDC</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>mdc</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>MDIO_I</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>mdio_in</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>MDIO_O</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>mdio_out</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>MDIO_T</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>mdio_tri</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.mdio_interface" xilinx:dependency="spirit:decode(id(&apos;PARAM_VALUE.Mdio_Management&apos;)) = 1">true</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>xgmii_interface</spirit:name>
      <spirit:displayName>xgmii_interface</spirit:displayName>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="xgmii" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="xgmii_rtl" spirit:version="1.0"/>
      <spirit:slave/>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RXC</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>xgmii_rxc</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RXD</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>xgmii_rxd</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>TXC</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>xgmii_txc</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>TXD</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>xgmii_txd</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>gt0_drp</spirit:name>
      <spirit:displayName>gt0_drp</spirit:displayName>
      <spirit:description>DRP Interface to Transceiver 0</spirit:description>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="drp" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="drp_rtl" spirit:version="1.0"/>
      <spirit:slave/>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>gt0_drpaddr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DEN</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>gt0_drpen</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DI</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>gt0_drpdi</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DO</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>gt0_drpdo</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DRDY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>gt0_drprdy</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DWE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>gt0_drpwe</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.gt0_drp" xilinx:dependency="spirit:decode(id(&apos;PARAM_VALUE.TransceiverControl&apos;) and ((starts_with(id(&apos;PARAM_VALUE.Transceiver&apos;),&apos;GTHE3&apos;)) or (starts_with(id(&apos;PARAM_VALUE.Transceiver&apos;),&apos;GTYE3&apos;)) or (starts_with(id(&apos;PARAM_VALUE.Transceiver&apos;),&apos;GTHE4&apos;))  or (starts_with(id(&apos;PARAM_VALUE.Transceiver&apos;),&apos;GTYE4&apos;))))">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>gt1_drp</spirit:name>
      <spirit:displayName>gt1_drp</spirit:displayName>
      <spirit:description>DRP Interface to Transceiver 1</spirit:description>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="drp" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="drp_rtl" spirit:version="1.0"/>
      <spirit:slave/>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>gt1_drpaddr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DEN</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>gt1_drpen</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DI</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>gt1_drpdi</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DO</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>gt1_drpdo</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DRDY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>gt1_drprdy</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DWE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>gt1_drpwe</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.gt1_drp" xilinx:dependency="spirit:decode(id(&apos;PARAM_VALUE.TransceiverControl&apos;) and ((starts_with(id(&apos;PARAM_VALUE.Transceiver&apos;),&apos;GTHE3&apos;)) or (starts_with(id(&apos;PARAM_VALUE.Transceiver&apos;),&apos;GTYE3&apos;)) or (starts_with(id(&apos;PARAM_VALUE.Transceiver&apos;),&apos;GTHE4&apos;))  or (starts_with(id(&apos;PARAM_VALUE.Transceiver&apos;),&apos;GTYE4&apos;))))">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>drp0</spirit:name>
      <spirit:displayName>drp0</spirit:displayName>
      <spirit:description>DRP Interface to Transceiver 0</spirit:description>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="drp" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="drp_rtl" spirit:version="1.0"/>
      <spirit:slave/>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>gt0_drpaddr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DEN</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>gt0_drpen</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DI</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>gt0_drpdi</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DO</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>gt0_drpdo</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DRDY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>gt0_drprdy</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DWE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>gt0_drpwe</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.drp0" xilinx:dependency="spirit:decode(id(&apos;PARAM_VALUE.TransceiverControl&apos;) and ((starts_with(id(&apos;PARAM_VALUE.Transceiver&apos;),&apos;GTXE2&apos;)) or (starts_with(id(&apos;PARAM_VALUE.Transceiver&apos;),&apos;GTHE2&apos;)) or (starts_with(id(&apos;PARAM_VALUE.Transceiver&apos;),&apos;GTPE2&apos;))))">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>drp1</spirit:name>
      <spirit:displayName>drp1</spirit:displayName>
      <spirit:description>DRP Interface to Transceiver 1</spirit:description>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="drp" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="drp_rtl" spirit:version="1.0"/>
      <spirit:slave/>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>gt1_drpaddr</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DEN</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>gt1_drpen</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DI</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>gt1_drpdi</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DO</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>gt1_drpdo</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DRDY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>gt1_drprdy</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>DWE</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>gt1_drpwe</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.drp1" xilinx:dependency="spirit:decode(id(&apos;PARAM_VALUE.TransceiverControl&apos;) and ((starts_with(id(&apos;PARAM_VALUE.Transceiver&apos;),&apos;GTXE2&apos;)) or (starts_with(id(&apos;PARAM_VALUE.Transceiver&apos;),&apos;GTHE2&apos;)) or (starts_with(id(&apos;PARAM_VALUE.Transceiver&apos;),&apos;GTPE2&apos;))))">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>dclk_port</spirit:name>
      <spirit:displayName>dclk</spirit:displayName>
      <spirit:description>DRP Clock - free running clock used to clock DRP and some logic.</spirit:description>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:slave/>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>dclk</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.DCLK_PORT.ASSOCIATED_BUSIF">drp0:drp1</spirit:value>
        </spirit:parameter>
      </spirit:parameters>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>refclk_diff_port</spirit:name>
      <spirit:displayName>refclk</spirit:displayName>
      <spirit:description>Differential GT reference clock</spirit:description>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock_rtl" spirit:version="1.0"/>
      <spirit:slave/>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK_N</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>refclk_n</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK_P</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>refclk_p</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.refclk_diff_port" xilinx:dependency="id(&apos;PARAM_VALUE.SupportLevel&apos;) = &apos;1&apos;">true</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>refclk_port</spirit:name>
      <spirit:displayName>refclk</spirit:displayName>
      <spirit:description>GT reference clock</spirit:description>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:slave/>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>refclk</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.refclk_port" xilinx:dependency="(((starts_with(id(&apos;PARAM_VALUE.Transceiver&apos;),&apos;GTXE2&apos;)) or (starts_with(id(&apos;PARAM_VALUE.Transceiver&apos;),&apos;GTHE2&apos;)) or (starts_with(id(&apos;PARAM_VALUE.Transceiver&apos;),&apos;GTHE3&apos;)) or (starts_with(id(&apos;PARAM_VALUE.Transceiver&apos;),&apos;GTYE3&apos;)) or (starts_with(id(&apos;PARAM_VALUE.Transceiver&apos;),&apos;GTHE4&apos;)) or (starts_with(id(&apos;PARAM_VALUE.Transceiver&apos;),&apos;GTYE4&apos;))) and (id(&apos;PARAM_VALUE.SupportLevel&apos;) = &apos;0&apos;))">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>refclk_out_port</spirit:name>
      <spirit:displayName>refclk_out</spirit:displayName>
      <spirit:description>Reference clock output from the differential transceiver clock buffer.</spirit:description>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>refclk_out</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.REFCLK_OUT_PORT.FREQ_HZ">156250000</spirit:value>
        </spirit:parameter>
      </spirit:parameters>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.refclk_out_port" xilinx:dependency="(((starts_with(id(&apos;PARAM_VALUE.Transceiver&apos;),&apos;GTXE2&apos;)) or (starts_with(id(&apos;PARAM_VALUE.Transceiver&apos;),&apos;GTHE2&apos;)) or (starts_with(id(&apos;PARAM_VALUE.Transceiver&apos;),&apos;GTHE3&apos;)) or (starts_with(id(&apos;PARAM_VALUE.Transceiver&apos;),&apos;GTYE3&apos;)) or (starts_with(id(&apos;PARAM_VALUE.Transceiver&apos;),&apos;GTHE4&apos;)) or (starts_with(id(&apos;PARAM_VALUE.Transceiver&apos;),&apos;GTYE4&apos;))) and (id(&apos;PARAM_VALUE.SupportLevel&apos;) = &apos;1&apos;))">true</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>clk156_out_port</spirit:name>
      <spirit:displayName>clk156_out</spirit:displayName>
      <spirit:description>156.25MHz output clock. Can be used to drive logic, but not another RXAUI instance.</spirit:description>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>clk156_out</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK156_OUT_PORT.ASSOCIATED_BUSIF">xgmii_interface</spirit:value>
        </spirit:parameter>
        <spirit:parameter>
          <spirit:name>FREQ_HZ</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK156_OUT_PORT.FREQ_HZ">156250000</spirit:value>
        </spirit:parameter>
      </spirit:parameters>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>qpll0outclk_out_port</spirit:name>
      <spirit:displayName>qpll0outclk_out</spirit:displayName>
      <spirit:description>Output from the quad PLL port QPLL0OUTCLK.</spirit:description>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>qpll0outclk_out</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.qpll0outclk_out_port" xilinx:dependency="(((starts_with(id(&apos;PARAM_VALUE.Transceiver&apos;),&apos;GTHE3&apos;)) or (starts_with(id(&apos;PARAM_VALUE.Transceiver&apos;),&apos;GTYE3&apos;)) or (starts_with(id(&apos;PARAM_VALUE.Transceiver&apos;),&apos;GTHE4&apos;)) or (starts_with(id(&apos;PARAM_VALUE.Transceiver&apos;),&apos;GTYE4&apos;))) and (id(&apos;PARAM_VALUE.SupportLevel&apos;) = &apos;1&apos;))">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>qpll0outrefclk_out_port</spirit:name>
      <spirit:displayName>qpll0outrefclk_out</spirit:displayName>
      <spirit:description>Output from the quad PLL port QPLL0OUTREFCLK.</spirit:description>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>qpll0outrefclk_out</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.qpll0outrefclk_out_port" xilinx:dependency="(((starts_with(id(&apos;PARAM_VALUE.Transceiver&apos;),&apos;GTHE3&apos;)) or (starts_with(id(&apos;PARAM_VALUE.Transceiver&apos;),&apos;GTYE3&apos;)) or (starts_with(id(&apos;PARAM_VALUE.Transceiver&apos;),&apos;GTYE4&apos;))) and (id(&apos;PARAM_VALUE.SupportLevel&apos;) = &apos;1&apos;))">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>qpll0outclk_port</spirit:name>
      <spirit:displayName>qpll0outclk</spirit:displayName>
      <spirit:description>Connect to the quad PLL output clock QPLL0OUTCLK.</spirit:description>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:slave/>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>qpll0outclk</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.qpll0outclk_port" xilinx:dependency="(((starts_with(id(&apos;PARAM_VALUE.Transceiver&apos;),&apos;GTHE3&apos;)) or (starts_with(id(&apos;PARAM_VALUE.Transceiver&apos;),&apos;GTYE3&apos;)) or (starts_with(id(&apos;PARAM_VALUE.Transceiver&apos;),&apos;GTHE4&apos;) or (starts_with(id(&apos;PARAM_VALUE.Transceiver&apos;),&apos;GTYE4&apos;)))) and (id(&apos;PARAM_VALUE.SupportLevel&apos;) = &apos;0&apos;))">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>qpll0outrefclk_port</spirit:name>
      <spirit:displayName>qpll0outrefclk</spirit:displayName>
      <spirit:description>Connect to the quad PLL output reference clock QPLL0OUTREFCLK.</spirit:description>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:slave/>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>qpll0outrefclk</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.qpll0outrefclk_port" xilinx:dependency="(((starts_with(id(&apos;PARAM_VALUE.Transceiver&apos;),&apos;GTHE3&apos;)) or (starts_with(id(&apos;PARAM_VALUE.Transceiver&apos;),&apos;GTYE3&apos;)) or (starts_with(id(&apos;PARAM_VALUE.Transceiver&apos;),&apos;GTHE4&apos;)) or (starts_with(id(&apos;PARAM_VALUE.Transceiver&apos;),&apos;GTYE4&apos;))) and (id(&apos;PARAM_VALUE.SupportLevel&apos;) = &apos;0&apos;))">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>qplloutclk_out_port</spirit:name>
      <spirit:displayName>qplloutclk_out</spirit:displayName>
      <spirit:description>Output from the quad PLL port QPLLOUTCLK.</spirit:description>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>qplloutclk_out</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.qplloutclk_out_port" xilinx:dependency="(((starts_with(id(&apos;PARAM_VALUE.Transceiver&apos;),&apos;GTXE2&apos;)) or (starts_with(id(&apos;PARAM_VALUE.Transceiver&apos;),&apos;GTHE2&apos;))) and (id(&apos;PARAM_VALUE.SupportLevel&apos;) = &apos;1&apos;))">true</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>qplloutclk_port</spirit:name>
      <spirit:displayName>qplloutclk</spirit:displayName>
      <spirit:description>Connect to the quad PLL output clock QPLLOUTCLK.</spirit:description>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:slave/>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>qplloutclk</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.qplloutclk_port" xilinx:dependency="(((starts_with(id(&apos;PARAM_VALUE.Transceiver&apos;),&apos;GTXE2&apos;)) or (starts_with(id(&apos;PARAM_VALUE.Transceiver&apos;),&apos;GTHE2&apos;))) and (id(&apos;PARAM_VALUE.SupportLevel&apos;) = &apos;0&apos;))">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>qplloutrefclk_out_port</spirit:name>
      <spirit:displayName>qplloutrefclk_out</spirit:displayName>
      <spirit:description>Output from the quad PLL port QPLLREFCLK.</spirit:description>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>qplloutrefclk_out</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.qplloutrefclk_out_port" xilinx:dependency="(((starts_with(id(&apos;PARAM_VALUE.Transceiver&apos;),&apos;GTXE2&apos;)) or (starts_with(id(&apos;PARAM_VALUE.Transceiver&apos;),&apos;GTHE2&apos;))) and (id(&apos;PARAM_VALUE.SupportLevel&apos;) = &apos;1&apos;))">true</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>qplloutrefclk_port</spirit:name>
      <spirit:displayName>qplloutrefclk</spirit:displayName>
      <spirit:description>Connect to the quad PLL output reference clock QPLLOUTREFCLK.</spirit:description>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:slave/>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>qplloutrefclk</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.qplloutrefclk_port" xilinx:dependency="(((starts_with(id(&apos;PARAM_VALUE.Transceiver&apos;),&apos;GTXE2&apos;)) or (starts_with(id(&apos;PARAM_VALUE.Transceiver&apos;),&apos;GTHE2&apos;))) and (id(&apos;PARAM_VALUE.SupportLevel&apos;) = &apos;0&apos;))">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>pll0outclk_out_port</spirit:name>
      <spirit:displayName>pll0outclk_out</spirit:displayName>
      <spirit:description>Output from the GTPE2_COMMON PLL port PLL0OUTCLK.</spirit:description>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>pll0outclk_out</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pll0outclk_out_port" xilinx:dependency="(starts_with(id(&apos;PARAM_VALUE.Transceiver&apos;),&apos;GTPE2&apos;) and (id(&apos;PARAM_VALUE.SupportLevel&apos;) = &apos;1&apos;))">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>pll0outclk_port</spirit:name>
      <spirit:displayName>pll0outclk</spirit:displayName>
      <spirit:description>Connect to the GTPE2_COMMON PLL port PLL0OUTCLK.</spirit:description>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:slave/>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>pll0outclk</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pll0outclk_port" xilinx:dependency="(starts_with(id(&apos;PARAM_VALUE.Transceiver&apos;),&apos;GTPE2&apos;) and (id(&apos;PARAM_VALUE.SupportLevel&apos;) = &apos;0&apos;))">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>pll0outrefclk_out_port</spirit:name>
      <spirit:displayName>pll0outrefclk_out</spirit:displayName>
      <spirit:description>Output from the GTPE2_COMMON PLL port PLL0OUTREFCLK</spirit:description>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>pll0outrefclk_out</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pll0outrefclk_out_port" xilinx:dependency="(starts_with(id(&apos;PARAM_VALUE.Transceiver&apos;),&apos;GTPE2&apos;) and (id(&apos;PARAM_VALUE.SupportLevel&apos;) = &apos;1&apos;))">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>pll0outrefclk_port</spirit:name>
      <spirit:displayName>pll0outrefclk</spirit:displayName>
      <spirit:description>Connect to the GTPE2_COMMON PLL REFCLK port PLL0OUTREFCLK</spirit:description>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:slave/>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>pll0outrefclk</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pll0outrefclk_port" xilinx:dependency="(starts_with(id(&apos;PARAM_VALUE.Transceiver&apos;),&apos;GTPE2&apos;) and (id(&apos;PARAM_VALUE.SupportLevel&apos;) = &apos;0&apos;))">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>pll1outclk_out_out_port</spirit:name>
      <spirit:displayName>pll1outclk_out</spirit:displayName>
      <spirit:description>Output from the GTPE2_COMMON PLL port PLL1OUTCLK.</spirit:description>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>pll1outclk_out</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pll1outclk_out_out_port" xilinx:dependency="(starts_with(id(&apos;PARAM_VALUE.Transceiver&apos;),&apos;GTPE2&apos;) and (id(&apos;PARAM_VALUE.SupportLevel&apos;) = &apos;1&apos;))">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>pll1outclk_port</spirit:name>
      <spirit:displayName>pll1outclk</spirit:displayName>
      <spirit:description>Connect to the GTPE2_COMMON PLL port PLL1OUTCLK.</spirit:description>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:slave/>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>pll1outclk</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pll1outclk_port" xilinx:dependency="(starts_with(id(&apos;PARAM_VALUE.Transceiver&apos;),&apos;GTPE2&apos;) and (id(&apos;PARAM_VALUE.SupportLevel&apos;) = &apos;0&apos;))">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>pll1outrefclk_out_port</spirit:name>
      <spirit:displayName>pll1outrefclk_out</spirit:displayName>
      <spirit:description>Output from the GTPE2_COMMON PLL port PLL1OUTREFCLK</spirit:description>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>pll1outrefclk_out</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pll1outrefclk_out_port" xilinx:dependency="(starts_with(id(&apos;PARAM_VALUE.Transceiver&apos;),&apos;GTPE2&apos;) and (id(&apos;PARAM_VALUE.SupportLevel&apos;) = &apos;1&apos;))">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>pll1outrefclk_port</spirit:name>
      <spirit:displayName>pll1outrefclk</spirit:displayName>
      <spirit:description>Connect to the GTPE2_COMMON PLL REFCLK port PLL1OUTREFCLK</spirit:description>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
      <spirit:slave/>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CLK</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>pll1outrefclk</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pll1outrefclk_port" xilinx:dependency="(starts_with(id(&apos;PARAM_VALUE.Transceiver&apos;),&apos;GTPE2&apos;) and (id(&apos;PARAM_VALUE.SupportLevel&apos;) = &apos;0&apos;))">false</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:busInterfaceInfo>
      </spirit:vendorExtensions>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>reset</spirit:name>
      <spirit:displayName>reset</spirit:displayName>
      <spirit:description>Asynchronous Reset</spirit:description>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:slave/>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>reset</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
      <spirit:parameters>
        <spirit:parameter>
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