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[/] [xmatchpro/] [trunk/] [xmw4-comdec/] [xmatch_sim7/] [coregen/] [DP_RAM_XILINX_256/] [simulation/] [timing/] [simulate_isim.bat] - Rev 9

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echo "Compiling Core VHDL UNISIM/Behavioral model"
vhpcomp  -work work ..\..\implement\results\routed.vhd

echo "Compiling Test Bench Files"

vhpcomp -work work    ..\bmg_tb_pkg.vhd
vhpcomp -work work    ..\random.vhd
vhpcomp -work work    ..\data_gen.vhd
vhpcomp -work work    ..\addr_gen.vhd
vhpcomp -work work    ..\checker.vhd
vhpcomp -work work    ..\bmg_stim_gen.vhd
vhpcomp -work work    ..\DP_RAM_XILINX_256_synth.vhd 
vhpcomp -work work    ..\DP_RAM_XILINX_256_tb.vhd


    fuse -L simprim work.DP_RAM_XILINX_256_tb -o DP_RAM_XILINX_256_tb.exe

.\DP_RAM_XILINX_256_tb.exe -sdftyp /DP_RAM_XILINX_256_tb/DP_RAM_XILINX_256_synth_inst/bmg_port=..\..\implement\results\routed.sdf -gui -tclbatch simcmds.tcl

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