URL https://opencores.org/ocsvn/xmatchpro/xmatchpro/trunk

Subversion Repositories xmatchpro

[/] [xmatchpro/] [trunk/] [xmw4-comdec/] [xmatch_sim7/] [ipcore_dir/] [DP_RAM_XILINX_512/] [simulation/] [timing/] [wave_ncsim.sv] - Rev 9

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window new WaveWindow  -name  "Waves for BMG Example Design"
waveform  using  "Waves for BMG Example Design"


      waveform add -signals /DP_RAM_XILINX_512_tb/status
      waveform add -signals /DP_RAM_XILINX_512_tb/DP_RAM_XILINX_512_synth_inst/bmg_port/CLKA
      waveform add -signals /DP_RAM_XILINX_512_tb/DP_RAM_XILINX_512_synth_inst/bmg_port/ADDRA
      waveform add -signals /DP_RAM_XILINX_512_tb/DP_RAM_XILINX_512_synth_inst/bmg_port/DINA
      waveform add -signals /DP_RAM_XILINX_512_tb/DP_RAM_XILINX_512_synth_inst/bmg_port/WEA
      waveform add -signals /DP_RAM_XILINX_512_tb/DP_RAM_XILINX_512_synth_inst/bmg_port/DOUTA
      waveform add -signals /DP_RAM_XILINX_512_tb/DP_RAM_XILINX_512_synth_inst/bmg_port/CLKB
      waveform add -signals /DP_RAM_XILINX_512_tb/DP_RAM_XILINX_512_synth_inst/bmg_port/ADDRB
      waveform add -signals /DP_RAM_XILINX_512_tb/DP_RAM_XILINX_512_synth_inst/bmg_port/ENB
      waveform add -signals /DP_RAM_XILINX_512_tb/DP_RAM_XILINX_512_synth_inst/bmg_port/DINB
      waveform add -signals /DP_RAM_XILINX_512_tb/DP_RAM_XILINX_512_synth_inst/bmg_port/WEB
      waveform add -signals /DP_RAM_XILINX_512_tb/DP_RAM_XILINX_512_synth_inst/bmg_port/DOUTB
console submit -using simulator -wait no "run"

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Subversion Repositories xmatchpro

[/] [xmatchpro/] [trunk/] [xmw4-comdec/] [xmatch_sim7/] [ipcore_dir/] [DP_RAM_XILINX_512/] [simulation/] [timing/] [wave_ncsim.sv] - Rev 9