URL https://opencores.org/ocsvn/xmatchpro/xmatchpro/trunk

Subversion Repositories xmatchpro

[/] [xmatchpro/] [trunk/] [xmw4-comdec/] [xmatch_sim7/] [ipcore_dir/] [DP_RAM_XILINX_MASK/] [simulation/] [timing/] [wave_mti.do] - Rev 9

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onerror {resume}
quietly WaveActivateNextPane {} 0


      add wave -noupdate /DP_RAM_XILINX_MASK_tb/status
      add wave -noupdate /DP_RAM_XILINX_MASK_tb/DP_RAM_XILINX_MASK_synth_inst/bmg_port/CLKA
      add wave -noupdate /DP_RAM_XILINX_MASK_tb/DP_RAM_XILINX_MASK_synth_inst/bmg_port/ADDRA
      add wave -noupdate /DP_RAM_XILINX_MASK_tb/DP_RAM_XILINX_MASK_synth_inst/bmg_port/DINA
      add wave -noupdate /DP_RAM_XILINX_MASK_tb/DP_RAM_XILINX_MASK_synth_inst/bmg_port/WEA
      add wave -noupdate /DP_RAM_XILINX_MASK_tb/DP_RAM_XILINX_MASK_synth_inst/bmg_port/DOUTA
      add wave -noupdate /DP_RAM_XILINX_MASK_tb/DP_RAM_XILINX_MASK_synth_inst/bmg_port/CLKB
      add wave -noupdate /DP_RAM_XILINX_MASK_tb/DP_RAM_XILINX_MASK_synth_inst/bmg_port/ADDRB
      add wave -noupdate /DP_RAM_XILINX_MASK_tb/DP_RAM_XILINX_MASK_synth_inst/bmg_port/ENB
      add wave -noupdate /DP_RAM_XILINX_MASK_tb/DP_RAM_XILINX_MASK_synth_inst/bmg_port/DINB
      add wave -noupdate /DP_RAM_XILINX_MASK_tb/DP_RAM_XILINX_MASK_synth_inst/bmg_port/WEB
      add wave -noupdate /DP_RAM_XILINX_MASK_tb/DP_RAM_XILINX_MASK_synth_inst/bmg_port/DOUTB
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {0 ps} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {0 ps} {9464063 ps}

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Subversion Repositories xmatchpro

[/] [xmatchpro/] [trunk/] [xmw4-comdec/] [xmatch_sim7/] [ipcore_dir/] [DP_RAM_XILINX_MASK/] [simulation/] [timing/] [wave_mti.do] - Rev 9