Subversion Repositories xulalx25soc

#**********************************************************************
# Copyright (c) 1997-2014 by XESS Corp <http://www.xess.com>.
# All rights reserved.
#
# This library is free software; you can redistribute it and/or
# modify it under the terms of the GNU Lesser General Public
# License as published by the Free Software Foundation; either
# version 3.0 of the License, or (at your option) any later version.
# 
# This library is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
# Lesser General Public License for more details.
# 
# You should have received a copy of the GNU Lesser General Public
# License along with this library.  If not, see 
# <http://www.gnu.org/licenses/>.
#**********************************************************************

NET i_clk_12mhz      LOC = A9;    # 12 MHz clock input.

##############################
# SDRAM
##############################
NET o_ram_cke        LOC = J12;
NET o_ram_clk        LOC = K11;
NET i_ram_feedback_clk      LOC = K12;
NET o_ram_cs_n       LOC = H4;
NET o_ram_ras_n      LOC = L4;
NET o_ram_cas_n      LOC = L3;
NET o_ram_we_n       LOC = M3;
NET o_ram_ldqm       LOC = M4;
NET o_ram_udqm       LOC = L13;
NET o_ram_bs<0>      LOC = H3;
NET o_ram_bs<1>      LOC = G3;
NET o_ram_addr<0>    LOC = E4;
NET o_ram_addr<1>    LOC = E3;
NET o_ram_addr<2>    LOC = D3;
NET o_ram_addr<3>    LOC = C3;
NET o_ram_addr<4>    LOC = B12;
NET o_ram_addr<5>    LOC = A12;
NET o_ram_addr<6>    LOC = D12;
NET o_ram_addr<7>    LOC = E12;
NET o_ram_addr<8>    LOC = G16;
NET o_ram_addr<9>    LOC = G12;
NET o_ram_addr<10>   LOC = F4;
NET o_ram_addr<11>   LOC = G11;
NET o_ram_addr<12>   LOC = H13;
NET io_ram_data<0>   LOC = P6;
NET io_ram_data<1>   LOC = T6;
NET io_ram_data<2>   LOC = T5;
NET io_ram_data<3>   LOC = P5;
NET io_ram_data<4>   LOC = R5;
NET io_ram_data<5>   LOC = N5;
NET io_ram_data<6>   LOC = P4;
NET io_ram_data<7>   LOC = N4;
NET io_ram_data<8>   LOC = P12;
NET io_ram_data<9>   LOC = R12;
NET io_ram_data<10>  LOC = T13;
NET io_ram_data<11>  LOC = T14;
NET io_ram_data<12>  LOC = R14;
NET io_ram_data<13>  LOC = T15;
NET io_ram_data<14>  LOC = T12;
NET io_ram_data<15>  LOC = P11;

##############################
# Flash
##############################
NET o_sd_cs_n      LOC = T8;
NET o_sf_cs_n      LOC = T3;
NET o_spi_sck      LOC = R11;
NET o_spi_mosi     LOC = T10;
NET i_spi_miso     LOC = P10;

##############################
# Prototyping Header
##############################
# NET io_chan_clk     LOC = T7;   # L32N
NET i_rx_uart     LOC = B15;   # L32P
NET i_gpio<0>     LOC = R15;  # L49P
NET i_gpio<1>     LOC = R16;  # L49N
NET i_gpio<2>     LOC = M15;  # L46P
NET i_gpio<3>     LOC = M16;  # L46N
NET i_gpio<4>     LOC = K15;  # L44P
NET i_gpio<5>     LOC = K16;  # L44N
NET i_gpio<6>     LOC = J16;  # L43N
NET i_gpio<7>     LOC = J14;  # L43P
NET i_gpio<8>     LOC = F15;  # L35P
NET i_gpio<9>     LOC = F16;  # L35N
NET i_gpio<10>    LOC = C16;  # L33N
NET i_gpio<11>    LOC = C15;  # L33P
NET i_gpio<12>    LOC = R2;  # L29N
NET i_gpio<13>    LOC = R7;  # L29P
NET o_pwm        LOC = T4;   # L63N (No differential pair!)
NET o_tx_uart    LOC = B16;   # L32P
NET o_gpio<0>    LOC = R1;   # L32N
NET o_gpio<1>    LOC = M2;   # L35P
NET o_gpio<2>    LOC = M1;   # L35N
NET o_gpio<3>    LOC = K3;   # L42P
NET o_gpio<4>    LOC = J4;   # L42N
NET o_gpio<5>    LOC = H1;   # L39N
NET o_gpio<6>    LOC = H2;   # L39P
NET o_gpio<7>    LOC = F1;   # L41N
NET o_gpio<8>    LOC = F2;   # L41P
NET o_gpio<9>    LOC = E1;   # L46N
NET o_gpio<10>    LOC = E2;   # L46P
NET o_gpio<11>    LOC = C1;   # L50P
NET o_gpio<12>    LOC = B1;   # L50N
NET o_gpio<13>    LOC = B2;   # L52P
NET o_gpio<14>    LOC = A2;   # L52N

##############################
# I/O Drive
##############################
NET i_clk_12mhz    IOSTANDARD = LVTTL;
NET o_ram_clk      IOSTANDARD = LVTTL | SLEW=FAST | DRIVE=8;
NET i_ram_feedback_clk      IOSTANDARD = LVTTL;
NET o_ram_cke      IOSTANDARD = LVTTL;
NET o_ram_cs_n     IOSTANDARD = LVTTL;
NET o_ram_addr*    IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=6;
NET o_ram_bs*      IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=6;
NET o_ram_ras_n    IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=6;
NET o_ram_cas_n    IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=6;
NET o_ram_we_n     IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=6;
NET io_ram_data*   IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=6;
NET o_ram_udqm     IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=6;
NET o_ram_ldqm     IOSTANDARD = LVTTL | SLEW=SLOW | DRIVE=6;
NET o_sd_cs_n      IOSTANDARD = LVTTL;
NET o_sf_cs_n      IOSTANDARD = LVTTL;
NET o_spi_sck      IOSTANDARD = LVTTL;
NET o_spi_mosi     IOSTANDARD = LVTTL;
NET i_gpio*        IOSTANDARD = LVTTL;
NET o_gpio*        IOSTANDARD = LVTTL;
NET o_pwm          IOSTANDARD = LVTTL;
NET o_tx_uart      IOSTANDARD = LVTTL;
NET i_rx_uart      IOSTANDARD = LVTTL;

##############################
# Clock Nets
##############################
NET "i_clk_12mhz" TNM_NET = "i_clk_12mhz";
NET "i_ram_feedback_clk" TNM_NET = "i_ram_feedback_clk";

#
# TimeSpec.  The source clock to the XuLA2-LX25 and LX9 boards is a 12MHz
# crystal oscillator.  12MHz corresponds to an 83.3333ns clocks---which would
# be the line below:
#
# (Please leave this commented ... I'll explain ...)
# TIMESPEC "TSi_clk_12mhz" = PERIOD "i_clk_12mhz" 83.333333 ns HIGH 50%;
# 
# However, ISE struggles to meet timing with this design.  By slightly
# adjusting the input clock speed faster in the hundreds of picoseconds range,
# I can create timing closure.  At one time, someone explained to me that I was
# really just forcing the XISE to use a different random seed for starting.
# This may well be the case, but ... it's worked for me so far.
TIMESPEC "TSi_clk_12mhz" = PERIOD "i_clk_12mhz" 83.1 ns HIGH 50%;
#
# The following line is included for completeness.  It is not used.
TIMESPEC "TSi_ram_feedback_clk" = PERIOD "i_ram_feedback_clk" 11.3 ns HIGH 50%;