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Subversion Repositories yavga
[/] [yavga/] [trunk/] [vhdl/] [s3e_starter_1600k.ucf] - Rev 24
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#################################################################################### ######## This file is part of the yaVGA project ######## http://www.opencores.org/?do=project&who=yavga ######## ######## Description ######## Implementation of yaVGA IP core ######## ######## To Do: ######## ######## ######## Author(s): ######## Sandro Amato, sdroamt@netscape.net ######## ######################################################################################## ######## Copyright (c) 2009, Sandro Amato ######## All rights reserved. ######## ######## Redistribution and use in source and binary forms, with or without ######## modification, are permitted provided that the following conditions ######## are met: ######## ######## * Redistributions of source code must retain the above ######## copyright notice, this list of conditions and the ######## following disclaimer. ######## * Redistributions in binary form must reproduce the above ######## copyright notice, this list of conditions and the ######## following disclaimer in the documentation and/or other ######## materials provided with the distribution. ######## * Neither the name of SANDRO AMATO nor the names of its ######## contributors may be used to endorse or promote products ######## derived from this software without specific prior written ######## permission. ######## ######## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ######## "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ######## LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ######## FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ######## COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ######## INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, ######## BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ######## LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ######## CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ######## LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ######## ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ######## POSSIBILITY OF SUCH DAMAGE. #####################################################################################PACE: Start of Constraints generated by PACE#PACE: Start of PACE I/O Pin AssignmentsNET "i_clk" LOC = "c9" | IOSTANDARD = LVCMOS33 ;NET "o_b" LOC = "g15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;NET "o_g" LOC = "h15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;NET "o_hsync" LOC = "f15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;NET "o_r" LOC = "h14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;NET "o_vsync" LOC = "f14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;#PACE: Start of PACE Area Constraints#AREA_GROUP "AG_u1_vga_ctrl" RANGE = SLICE_X84Y109:SLICE_X89Y100 ;#INST "u1_vga_ctrl" AREA_GROUP = "AG_u1_vga_ctrl" ;#PACE: Start of PACE Prohibit Constraints#PACE: End of Constraints generated by PACENET "i_clk" TNM_NET = i_clk;TIMESPEC TS_i_clk = PERIOD "i_clk" 20 ns HIGH 40%;