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[/] [z80soc/] [trunk/] [V0.7.3/] [DE1/] [db/] [mux_hib.tdf] - Rev 46

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--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone II" LPM_SIZE=2 LPM_WIDTH=8 LPM_WIDTHS=1 data result sel
--VERSION_BEGIN 13.0 cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ  VERSION_END


-- Copyright (C) 1991-2013 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.



--synthesis_resources = lut 8 
SUBDESIGN mux_hib
( 
        data[15..0]     :       input;
        result[7..0]    :       output;
        sel[0..0]       :       input;
) 
VARIABLE 
        result_node[7..0]       : WIRE;
        sel_node[0..0]  : WIRE;
        w_data244w[1..0]        : WIRE;
        w_data258w[1..0]        : WIRE;
        w_data270w[1..0]        : WIRE;
        w_data282w[1..0]        : WIRE;
        w_data294w[1..0]        : WIRE;
        w_data306w[1..0]        : WIRE;
        w_data318w[1..0]        : WIRE;
        w_data330w[1..0]        : WIRE;

BEGIN 
        result[] = result_node[];
        result_node[] = ( ((sel_node[] & w_data330w[1..1]) # ((! sel_node[]) & w_data330w[0..0])), ((sel_node[] & w_data318w[1..1]) # ((! sel_node[]) & w_data318w[0..0])), ((sel_node[] & w_data306w[1..1]) # ((! sel_node[]) & w_data306w[0..0])), ((sel_node[] & w_data294w[1..1]) # ((! sel_node[]) & w_data294w[0..0])), ((sel_node[] & w_data282w[1..1]) # ((! sel_node[]) & w_data282w[0..0])), ((sel_node[] & w_data270w[1..1]) # ((! sel_node[]) & w_data270w[0..0])), ((sel_node[] & w_data258w[1..1]) # ((! sel_node[]) & w_data258w[0..0])), ((sel_node[] & w_data244w[1..1]) # ((! sel_node[]) & w_data244w[0..0])));
        sel_node[] = ( sel[0..0]);
        w_data244w[] = ( data[8..8], data[0..0]);
        w_data258w[] = ( data[9..9], data[1..1]);
        w_data270w[] = ( data[10..10], data[2..2]);
        w_data282w[] = ( data[11..11], data[3..3]);
        w_data294w[] = ( data[12..12], data[4..4]);
        w_data306w[] = ( data[13..13], data[5..5]);
        w_data318w[] = ( data[14..14], data[6..6]);
        w_data330w[] = ( data[15..15], data[7..7]);
END;
--VALID FILE

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