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[/] [zap/] [trunk/] [src/] [ts/] [arm_test/] [Config.cfg] - Rev 43

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# TC config.

%Config = ( 
        # CPU configuration.
        DATA_CACHE_SIZE             => 4096,    # Data cache size in bytes
        CODE_CACHE_SIZE             => 4096,    # Instruction cache size in bytes
        CODE_SECTION_TLB_ENTRIES    => 8,       # Instruction section TLB entries.
        CODE_SPAGE_TLB_ENTRIES      => 32,      # Instruction small page TLB entries.
        CODE_LPAGE_TLB_ENTRIES      => 16,      # Instruction large page TLB entries.
        DATA_SECTION_TLB_ENTRIES    => 8,       # Data section TLB entries.
        DATA_SPAGE_TLB_ENTRIES      => 32,      # Data small page TLB entries.
        DATA_LPAGE_TLB_ENTRIES      => 16,      # Data large page TLB entries.
        BP_DEPTH                    => 1024,    # Branch predictor depth.
        INSTR_FIFO_DEPTH            => 4,       # Instruction buffer depth.
        STORE_BUFFER_DEPTH          => 16,      # Store buffer depth.
        SYNTHESIS                   => 0,       # 0 allows debug messages.

        # Testbench configuration.
        WAVES                       => 0,       # Log VCD
        EXT_RAM_SIZE                => 32768,   # External RAM size.
        SEED                        => -1,      # Seed. Use -1 to use random seed.
        DUMP_START                  => 2000,    # Starting memory address from which to dump.
        DUMP_SIZE                   => 200,     # Length of dump in bytes.
        MAX_CLOCK_CYCLES            => 40000,   # Clock cycles to run the simulation for.
        DEFINE_TLB_DEBUG            => 0,       # Make this 1 to define TLB_DEBUG. Useful for debugging the TLB.
        REG_CHECK                   => {
                                                # Value of registers(Post Translate) at the end of the test.
                                                # "r<regNumber> => Verilog_value"
                                                "r0"  => "32'hFFFFFFFF",
                                                "r1"  => "32'hFFFFFFFF",
                                                "r2"  => "32'hFFFFFFFF",
                                                "r3"  => "32'hFFFFFFFF",
                                                "r4"  => "32'hFFFFFFFF",
                                                "r5"  => "32'hFFFFFFFF",
                                                "r6"  => "32'hFFFFFFFF",
                                                "r7"  => "32'hFFFFFFFF",
                                                "r8"  => "32'hFFFFFFFF",
                                                "r9"  => "32'hFFFFFFFF",
                                                "r10" => "32'hFFFFFFFF",
                                                "r11" => "32'hFFFFFFFF",
                                                "r12" => "32'hFFFFFFFF",
                                                "r13" => "32'hFFFFFFFF",
                                                "r14" => "32'hFFFFFFFF"
                                       },
        FINAL_CHECK                 => {}
);

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