OpenCores
URL https://opencores.org/ocsvn/zap/zap/trunk

Subversion Repositories zap

[/] [zap/] [trunk/] [src/] [ts/] [factorial/] [Config.cfg] - Rev 38

Go to most recent revision | Compare with Previous | Blame | View Log

# TC config.

%Config = ( 
        # CPU configuration.
        DATA_CACHE_SIZE             => 4096,    # Data cache size in bytes
        CODE_CACHE_SIZE             => 4096,    # Instruction cache size in bytes
        CODE_SECTION_TLB_ENTRIES    => 512,     # Instruction section TLB entries.
        CODE_SPAGE_TLB_ENTRIES      => 512,     # Instruction small page TLB entries.
        CODE_LPAGE_TLB_ENTRIES      => 512,     # Instruction large page TLB entries.
        DATA_SECTION_TLB_ENTRIES    => 512,     # Data section TLB entries.
        DATA_SPAGE_TLB_ENTRIES      => 512,     # Data small page TLB entries.
        DATA_LPAGE_TLB_ENTRIES      => 512,     # Data large page TLB entries.
        BP_DEPTH                    => 1024,    # Branch predictor depth.
        INSTR_FIFO_DEPTH            => 4,       # Instruction buffer depth.
        STORE_BUFFER_DEPTH          => 16,      # Store buffer depth.
        SYNTHESIS                   => 0,       # 0 allows debug messages.

        # Testbench configuration.
        IRQ_EN                      => 1,       # Enable IRQs.
        UART_TX_TERMINAL            => 0,       # No UART terminal.
        EXT_RAM_SIZE                => 32768,   # External RAM size.
        SEED                        => -1,      # Seed. Use -1 to use random seed.
        DUMP_START                  => 2000,    # Starting memory address from which to dump.
        DUMP_SIZE                   => 200,     # Length of dump in bytes.
        MAX_CLOCK_CYCLES            => 100000,  # Clock cycles to run the simulation for.
        ALLOW_STALLS                => 0,       # Make this 1 to allow external RAM to signal a stall.
        DEFINE_TLB_DEBUG            => 0,       # Make this 1 to define TLB_DEBUG. Useful for debugging the TLB.
        REG_CHECK                   => {},      # Registers to examine.
        FINAL_CHECK                 => {
                                                # Values of memory for test to succeed.
                                                # LOCATION => VALUE
                                                "32'd2000" => "32'h00007805",
                                                "32'd2004" => "32'h4048f5c3",
                                                "32'd2008" => "32'h00000001",
                                                "32'd2012" => "32'h00000000",
                                                "32'd2016" => "32'h00000001",
                                                "32'd2020" => "32'hfffffffe",
                                                "32'd2024" => "32'h00000001",
                                                "32'd2028" => "32'h00000001",
                                                "32'd2032" => "32'hfffffffe",
                                                "32'd2036" => "32'h00000001",
                                                "32'd2040" => "32'h00000000",
                                                "32'd2044" => "32'h00000001"
                                       }
);

##########################
#                        #        
# END OF FILE            #
#                        #
##########################

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.