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[/] [zet86/] [trunk/] [sim/] [signmul17.v] - Rev 53

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module signmul17 (
    input clk,
 
    input      signed [16:0] a,
    input      signed [16:0] b,
    output reg signed [33:0] p
  );
 
  // Behaviour
  always @(posedge clk) p <= a * b;
endmodule
 

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