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https://opencores.org/ocsvn/zx_ula/zx_ula/trunk
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[/] [zx_ula/] [branches/] [xilinx/] [ulaplus_replacement-upgrade_for_sp16-48k/] [rtl_ulaplus/] [coregen_xil_3244_19.cgp] - Rev 29
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# Date: Tue Sep 25 16:31:44 2012
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc5vlx20t
SET devicefamily = virtex5
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = ff323
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = false
SET vhdlsim = true
SET workingdirectory = ./tmp/
# CRC: e2b133ab
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