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[/] [zx_ula/] [branches/] [xilinx/] [ulaplus_replacement-upgrade_for_sp16-48k/] [rtl_ulaplus/] [rgb_builder.v] - Rev 26
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`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 11:10:16 04/04/2012 // Design Name: // Module Name: rgb_builder // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module rgb_builder( input reset, input select, // 0=ULA, 1=ULA+ input ri, // input gi, // digital IRGB input bi, // inputs from standar ULA input hi, // input [7:0] rgbulap, // 8-bit input from ULA+ output reg [2:0] r, // output reg [2:0] g, // 3-bit final RGB signals output reg [2:0] b // ); always @(*) begin if (!select) begin case ({hi,ri}) 2'b00 : r = 3'b000; 2'b01 : r = 3'b101; 2'b10 : r = 3'b000; 2'b11 : r = 3'b111; endcase end else r = rgbulap[4:2]; end always @(*) begin if (!select) begin case ({hi,gi}) 2'b00 : g = 3'b000; 2'b01 : g = 3'b101; 2'b10 : g = 3'b000; 2'b11 : g = 3'b111; endcase end else g = rgbulap[7:5]; end always @(*) begin if (!select) begin case ({hi,bi}) 2'b00 : b = 3'b000; 2'b01 : b = 3'b101; 2'b10 : b = 3'b000; 2'b11 : b = 3'b111; endcase end else b = {rgbulap[1:0],rgbulap[1]}; end endmodule