Subversion Repositories zx_ula

<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">

  <!--                                                          -->

  <!--             For tool use only. Do not edit.              -->

  <!--                                                          -->

  <!-- ProjectNavigator created generated project file.         -->

  <!-- For use in tracking generated file and other information -->

  <!-- allowing preservation of process status.                 -->

  <!--                                                          -->

  <!-- Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved. -->

  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>

  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="isim_test_for_ula.xise"/>

  <files xmlns="http://www.xilinx.com/XMLSchema">
    <file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/>
    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
    <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="test_standard_ula_beh.prj"/>
    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="test_standard_ula_isim_beh.exe"/>
    <file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="test_standard_ula_isim_beh.wdb"/>
    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="test_ulaplus_isim_beh.exe"/>
    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
  </files>

  <transforms xmlns="http://www.xilinx.com/XMLSchema">
    <transform xil_pn:end_ts="1336010207" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1336010207">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1336010207" xil_pn:in_ck="-2309135012432528930" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1336010207">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
      <outfile xil_pn:name="cpu.v"/>
      <outfile xil_pn:name="ram64bytes.v"/>
      <outfile xil_pn:name="test_ula.v"/>
      <outfile xil_pn:name="test_ulaplus.v"/>
      <outfile xil_pn:name="ula.v"/>
      <outfile xil_pn:name="ula_with_timex_hicolor_support_and_ulaplus.v"/>
    </transform>
    <transform xil_pn:end_ts="1336010207" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="875212791152153064" xil_pn:start_ts="1336010207">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1336010207" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="3749123271480189344" xil_pn:start_ts="1336010207">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1336010207" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-8927689239076426929" xil_pn:start_ts="1336010207">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1336010208" xil_pn:in_ck="-2309135012432528930" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1336010207">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
      <outfile xil_pn:name="cpu.v"/>
      <outfile xil_pn:name="ram64bytes.v"/>
      <outfile xil_pn:name="test_ula.v"/>
      <outfile xil_pn:name="test_ulaplus.v"/>
      <outfile xil_pn:name="ula.v"/>
      <outfile xil_pn:name="ula_with_timex_hicolor_support_and_ulaplus.v"/>
    </transform>
    <transform xil_pn:end_ts="1336010209" xil_pn:in_ck="-2309135012432528930" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="2042709971059340972" xil_pn:start_ts="1336010208">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
      <status xil_pn:value="OutOfDateForOutputs"/>
      <status xil_pn:value="OutputChanged"/>
      <outfile xil_pn:name="fuse.log"/>
      <outfile xil_pn:name="isim"/>
      <outfile xil_pn:name="isim.log"/>
      <outfile xil_pn:name="test_standard_ula_beh.prj"/>
      <outfile xil_pn:name="test_standard_ula_isim_beh.exe"/>
      <outfile xil_pn:name="xilinxsim.ini"/>
    </transform>
    <transform xil_pn:end_ts="1336010209" xil_pn:in_ck="-4675410216792265356" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-4549589325037546733" xil_pn:start_ts="1336010209">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
      <status xil_pn:value="OutOfDateForOutputs"/>
      <status xil_pn:value="OutputChanged"/>
      <outfile xil_pn:name="isim.cmd"/>
      <outfile xil_pn:name="isim.log"/>
      <outfile xil_pn:name="test_standard_ula_isim_beh.wdb"/>
    </transform>
  </transforms>

</generated_project>