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URL https://opencores.org/ocsvn/cop/cop/trunk

Subversion Repositories cop

[/] [cop/] [trunk/] [rtl/] [verilog/] - Rev 13

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Last modification

  • Rev 12 2010-01-27 20:28:09 GMT
  • Author: rehayes
  • Log message:
    Change WISHBONE ack signal so no output is generated when wait states are enabled and the bus transaction is terminated in the first cycle.
Path Last modification Log RSS feed
[FOLDER] cop/ 13  4926d 10h rehayes View Log RSS feed
[NODE][FOLDER] branches/ 1  5773d 19h root View Log RSS feed
[NODE][FOLDER] tags/ 1  5773d 19h root View Log RSS feed
[NODE][FOLDER] trunk/ 13  4926d 10h rehayes View Log RSS feed
[NODE][NODE][FOLDER] bench/ 10  5663d 10h rehayes View Log RSS feed
[NODE][NODE][FOLDER] doc/ 11  5524d 07h rehayes View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 13  4926d 10h rehayes View Log RSS feed
[NODE][NODE][NODE][FOLDER] sys_verilog/ 13  4926d 10h rehayes View Log RSS feed
[NODE][NODE][NODE][FOLDER] verilog/ 12  5524d 07h rehayes View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] cop_count.v 2  5749d 07h rehayes View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] cop_regs.v 9  5732d 08h rehayes View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] cop_top.v 9  5732d 08h rehayes View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] cop_wb_bus.v 12  5524d 07h rehayes View Log RSS feed
[NODE][NODE][FOLDER] sim/ 6  5749d 07h rehayes View Log RSS feed
[NODE][FOLDER] web_uploads/ 1  5773d 19h root View Log RSS feed

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