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[/] [minsoc/] [branches/] [verilator/] [sim/] [verilator/] - Rev 175

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  • Rev 140 2011-11-22 10:11:38 GMT
  • Author: rfajardo
  • Log message:
    Including required modules for verilator simulation.
Path Last modification Log RSS feed
[FOLDER] minsoc/ 175  4223d 16h rfajardo View Log RSS feed
[NODE][FOLDER] branches/ 153  4755d 00h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] rc-1.0/ 152  4755d 00h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] verilator/ 153  4755d 00h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] backend/ 137  4762d 00h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] bench/ 140  4761d 01h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] doc/ 101  4823d 04h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] prj/ 133  4776d 01h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] rtl/ 140  4761d 01h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] sim/ 140  4761d 01h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] modelsim/ 134  4776d 00h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] results/ 2  5555d 23h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] run/ 133  4776d 01h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] verilator/ 140  4761d 01h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] generate_verilator_bench 140  4761d 01h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] run_verilator_bench 140  4761d 01h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] sw/ 133  4776d 01h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] syn/ 121  4786d 15h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] utils/ 153  4755d 00h rfajardo View Log RSS feed
[NODE][FOLDER] tags/ 172  4307d 17h rfajardo View Log RSS feed
[NODE][FOLDER] trunk/ 175  4223d 16h rfajardo View Log RSS feed

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