URL https://opencores.org/ocsvn/test_project/test_project/trunk

Subversion Repositories test_project

[/] [test_project/] [trunk/] [rtl/] [verilog/] - Rev 88

Rev 54 2009-05-20 13:38:53 GMT
Author: julius
Log message:
Added verilog UART decoder for event-driven sim tests (icarus, nc) - removed MAC tests from multiplier tests - not returning right results for some reason - should be looked at

Path	Last modification			Log	RSS feed
test_project/	88	2895d 06h	marcus.erlandsson	View Log	RSS feed
branches/	10	5717d 17h	unneback	View Log	RSS feed
tags/	4	5739d 16h	root	View Log	RSS feed
trunk/	88	2895d 06h	marcus.erlandsson	View Log	RSS feed
backend/	22	5688d 16h	julius	View Log	RSS feed
bench/	55	5668d 11h	julius	View Log	RSS feed
linux_sd_driver/	82	5598d 02h	tac2	View Log	RSS feed
rtl/	54	5668d 12h	julius	View Log	RSS feed
verilog/	54	5668d 12h	julius	View Log	RSS feed
components/	48	5673d 06h	julius	View Log	RSS feed
dummy_slave.v	17	5689d 15h	unneback	View Log	RSS feed
eth_defines.v	17	5689d 15h	unneback	View Log	RSS feed
intercon.vm	20	5689d 15h	unneback	View Log	RSS feed
or1200_defines.v	33	5685d 01h	julius	View Log	RSS feed
orpsoc_top.v	54	5668d 12h	julius	View Log	RSS feed
uart_defines.v	17	5689d 15h	unneback	View Log	RSS feed
sim/	60	5667d 08h	julius	View Log	RSS feed
sw/	60	5667d 08h	julius	View Log	RSS feed
web_uploads/	6	5739d 10h	root	View Log	RSS feed