URL https://opencores.org/ocsvn/test_project/test_project/trunk

Subversion Repositories test_project

[/] [test_project/] [trunk/] [rtl/] [verilog/] - Rev 88

Rev 54 2009-05-20 13:38:53 GMT
Author: julius
Log message:
Added verilog UART decoder for event-driven sim tests (icarus, nc) - removed MAC tests from multiplier tests - not returning right results for some reason - should be looked at

Path	Last modification			Log	RSS feed
test_project/	88	3020d 09h	marcus.erlandsson	View Log	RSS feed
branches/	10	5842d 20h	unneback	View Log	RSS feed
tags/	4	5864d 19h	root	View Log	RSS feed
trunk/	88	3020d 09h	marcus.erlandsson	View Log	RSS feed
backend/	22	5813d 19h	julius	View Log	RSS feed
bench/	55	5793d 14h	julius	View Log	RSS feed
linux_sd_driver/	82	5723d 05h	tac2	View Log	RSS feed
rtl/	54	5793d 15h	julius	View Log	RSS feed
verilog/	54	5793d 15h	julius	View Log	RSS feed
components/	48	5798d 10h	julius	View Log	RSS feed
dummy_slave.v	17	5814d 18h	unneback	View Log	RSS feed
eth_defines.v	17	5814d 18h	unneback	View Log	RSS feed
intercon.vm	20	5814d 18h	unneback	View Log	RSS feed
or1200_defines.v	33	5810d 05h	julius	View Log	RSS feed
orpsoc_top.v	54	5793d 15h	julius	View Log	RSS feed
uart_defines.v	17	5814d 18h	unneback	View Log	RSS feed
sim/	60	5792d 11h	julius	View Log	RSS feed
sw/	60	5792d 11h	julius	View Log	RSS feed
web_uploads/	6	5864d 13h	root	View Log	RSS feed