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[/] - Rev 167
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Last modification
- Rev 167 2013-09-18 01:42:00 GMT
- Author: jshamlet
- Log message:
- Updated CPU model; Pipelined ALU control signals to improve fMAX, corrected issue with interrupt controller priority not being obeyed, fixed bug in auto-indexing instructions where the upper register wasn't being properly incremented, cleaned up code to make the processor model easier to follow.
Added several useful modules that use the Open8 bus.