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[/] - Rev 223
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Last modification
- Rev 223 2020-04-15 22:12:24 GMT
- Author: jshamlet
- Log message:
- Added an OPEN8_BUS_TYPE record to simplify connection to Open8 modules. The CPU now passes and Open8_Bus out, which supplies the bus address, write enable, write data, and read enable. Read data and interrupts are still handled as separate signals, since they are muxed/connected at the next level up.