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[/] - Rev 15
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Last modification
- Rev 15 2007-01-06 00:06:19 GMT
- Author: cwalter
- Log message:
- - Added second register locking port reg_lock1.
- Added function to check if the instruction modifies the SR register.
- Fetch of SR now checks if the SR is modified and if yes the SR register
is marked as locked.
- Stall signal for pipeline is now generated correctly.
- Stall input is now checked. If asserted the current output values are hold
until the stall signal is deasserted.