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Last modification

  • Rev 42 2007-01-12 23:15:22 GMT
  • Author: jlechner
  • Log message:
    Modified input signals for register locking (testbench modifications):
    Since id-stage and write-back-stage may have to lock or unlock two registers in one cycle
    there are now seperate locking and unlocking adress inputs (two ports for locking/ two for unlocking).
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