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[/] - Rev 12

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Last modification

  • Rev 12 2012-02-25 10:48:40 GMT
  • Author: motilito
  • Log message:
    Updated Verilog implementation to sync with VHDL to include internal bus request/grant mechanism.
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[FOLDER] uart2bus/ 12  4655d 22h motilito View Log RSS feed

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