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[/] [System09/] [trunk/] [rtl/] [VHDL/] - Rev 197
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Last modification
- Rev 197 2021-01-30 01:40:19 GMT
- Author: davidgb
- Log message:
- Updates from John Kent:
-- 4.5 John Kent 2012-02-04 Re-arranged Rx & Tx Baud clock edge detect.
-- 4.6 John Kent 3021-01-30 Double sample RxC, TxC, and RxD with cpu_clk
-- for 125MHz Clock on Zybo Z7 board.