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[/] [amber/] [trunk/] [hw/] [tools/] - Rev 54

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Last modification

  • Rev 54 2011-09-14 19:48:25 GMT
  • Author: csantifort
  • Log message:
    Bug fix for bug reported by Botao Lee. The mode bits in the decode stage did not change immediately
    after a mode switch from a teqp instruction, but 1 cycle later. This meant the wrong set of registers
    was selected for writing to for 1 clock cycle.
Path Last modification Log RSS feed
[FOLDER] amber/ 54  4823d 16h csantifort View Log RSS feed
[NODE][FOLDER] branches/ 1  5088d 21h root View Log RSS feed
[NODE][FOLDER] tags/ 1  5088d 21h root View Log RSS feed
[NODE][FOLDER] trunk/ 54  4823d 16h csantifort View Log RSS feed
[NODE][NODE][FOLDER] doc/ 48  4883d 20h csantifort View Log RSS feed
[NODE][NODE][FOLDER] hw/ 54  4823d 16h csantifort View Log RSS feed
[NODE][NODE][NODE][FOLDER] fpga/ 43  4911d 16h csantifort View Log RSS feed
[NODE][NODE][NODE][FOLDER] sim/ 43  4911d 16h csantifort View Log RSS feed
[NODE][NODE][NODE][FOLDER] tests/ 54  4823d 16h csantifort View Log RSS feed
[NODE][NODE][NODE][FOLDER] tools/ 54  4823d 16h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] all.sh 54  4823d 16h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] get_timeout.sh 15  5031d 08h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] run.sh 48  4883d 20h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] set_timeout.sh 15  5031d 08h csantifort View Log RSS feed
[NODE][NODE][NODE][FOLDER] vlog/ 54  4823d 16h csantifort View Log RSS feed
[NODE][NODE][FOLDER] sw/ 51  4879d 13h csantifort View Log RSS feed

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